{"push_id":951271224,"size":47,"distinct_size":1,"ref":"refs/heads/ti-lsk-linux-4.1.y","head":"08ad1740b59cc3aef52a2612b1e807a3e844583c","before":"38d595331e7daa6a2931babc0b10aab0d7270837","commits":[{"sha":"048779c80af5aa8f7f887424306481c4b9ed66a1","author":{"email":"c1574519d727edaf2e16b260e452051ef77bf018@ti.com","name":"Lokesh Vutla"},"message":"ti_config_fragments/baseport: Make crypto drivers as modules\n\nConverting crypto drivers to modules instead of built in, so that\nthese IPs can be inserted and removed dynamically for comparing the\nsw and hw crypto performances in a single boot.\n\nReported-by: Aparna Balasubramanian <aparnab@ti.com>\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/048779c80af5aa8f7f887424306481c4b9ed66a1"},{"sha":"061367bda03bebffcd94d227b7b498ae0800e860","author":{"email":"e5c0b4cdf99ae1d408b9c497159e74b54e02e008@ti.com","name":"Peter Ujfalusi"},"message":"dmaengine: omap-dma: Clean up the prep_slave_sg sg list walk code\n\ncommit e8a5e79c17f977d1820ffe9b6ac259c953b3b34b upstream.\n\nThe for_each_sg() macro's last parameter is inteded to be used as counter.\nWe can use 'i' instead of 'j' within the loop for indexes.\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Vinod Koul <vinod.koul@intel.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/061367bda03bebffcd94d227b7b498ae0800e860"},{"sha":"5b5f8b7e10fed653c5e34e67b8e0ff35ede914b2","author":{"email":"e5c0b4cdf99ae1d408b9c497159e74b54e02e008@ti.com","name":"Peter Ujfalusi"},"message":"dmaengine: omap-dma: Remove tasklet to start the transfers\n\ncommit 1c1d25f9f933211b622b0e209716372480051361 upstream.\n\nThe use of tasklet to actually start the DMA transfer slightly decreases the\nDMA throughput since it adds small scheduling delay when the transfer is\nstarted. In normal use, even with high I/O load the tasklet would start\none transaction at a time, however running the DMAtest for memcpy on all\navailable channels will cause the tasklet to start about 15 transfers.\nThe performance numbers on OMAP4 PandaBoard-es (test_buf_size = 6553):\nWith the tasklet:\ndmatest: dma0chan30-copy: summary 5000 tests, 0 failures 186 iops 593 KB/s (0)\ndmatest: dma0chan8-copy0: summary 5000 tests, 0 failures 184 iops 584 KB/s (0)\ndmatest: dma0chan13-copy: summary 5000 tests, 0 failures 184 iops 585 KB/s (0)\ndmatest: dma0chan12-copy: summary 5000 tests, 0 failures 184 iops 585 KB/s (0)\ndmatest: dma0chan7-copy0: summary 5000 tests, 0 failures 183 iops 581 KB/s (0)\n\nWith this patch (no tasklet):\ndmatest: dma0chan4-copy0: summary 5000 tests, 0 failures 199 iops 644 KB/s (0)\ndmatest: dma0chan5-copy0: summary 5000 tests, 0 failures 199 iops 645 KB/s (0)\ndmatest: dma0chan6-copy0: summary 5000 tests, 0 failures 199 iops 637 KB/s (0)\ndmatest: dma0chan24-copy: summary 5000 tests, 0 failures 199 iops 638 KB/s (0)\ndmatest: dma0chan16-copy: summary 5000 tests, 0 failures 199 iops 638 KB/s (0)\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Vinod Koul <vinod.koul@intel.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/5b5f8b7e10fed653c5e34e67b8e0ff35ede914b2"},{"sha":"b072f0b20f1993e68d75fdd1d7aa190ea56545e9","author":{"email":"e5c0b4cdf99ae1d408b9c497159e74b54e02e008@TI.COM","name":"Peter Ujfalusi"},"message":"dmaengine: omap-dma: Handle cases when the channel is polled for completion\n\ncommit 1a7cf7b26f2594bb1c622f76765f77d3a5140293 upstream.\n\nWhen a DMA client driver decides that it is not providing callback for\ncompletion of a transfer (and/or does not set the DMA_PREP_INTERRUPT) but\nit will poll the status of the transfer (in case of short memcpy for\nexample) we will not get interrupt for the completion of the transfer and\nwill not mark the transaction as done.\nCheck the channel enable bit in the CCR when the status is queried and if\nthe channel is no longer active, we call the omap_dma_callback() to handle\nthe transfer completion.\n\nSigned-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>\nSigned-off-by: Vinod Koul <vinod.koul@intel.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b072f0b20f1993e68d75fdd1d7aa190ea56545e9"},{"sha":"3c862d1f48a551a21b13b52fc1a56d831922f10e","author":{"email":"c224db9378a929ae8338a052bbb1b30fb46cdd39@ti.com","name":"Kishon Vijay Abraham I"},"message":"regulator: palmas: Disable bypass for ldo1 and ldo2\n\nldo1 and ldo2 have bypass capability. The regulator framework starts\nwith assuming that bypass is disabled by default. In this particular\ncase the bypass OTP is 1. So one cannot disable without first enabling\ndue to the use count going negative. Hence doing a one time disable at\nboot.\n\nAny consumer which wants bypass to be enabled/disabled can use the\nbypass_enable/bypass_disable functions to turn on or turn off bypass\nsubsequently.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>\nSigned-off-by: Kishon Vijay Abraham I <kishon@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/3c862d1f48a551a21b13b52fc1a56d831922f10e"},{"sha":"f43d695ccf2259a8c8960e734a348e7f46984abc","author":{"email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com","name":"Grygorii Strashko"},"message":"config_fragments: am33/am43: disable CONFIG_CPUSETS\n\nIt makes no sense to enable CONFIG_CPUSETS on UP systems and\nCONFIG_CPUSETS disabling will remove just few more code from\nscheduler's hot path.\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/f43d695ccf2259a8c8960e734a348e7f46984abc"},{"sha":"ecc64c5e3a0be3761da221da137197fd60834735","author":{"email":"1001e8702733cced254345e193c88aaa47a4f5de@atomide.com","name":"Tony Lindgren"},"message":"ARM: OMAP2+: Fix imprecise external abort caused by bogus SRAM init\n\ncommit 57df5380853460bc66b59a46273ce113c923d39c upstream.\n\nSome omaps are producing imprecise external aborts because we are\nwrongly trying to init SRAM for device tree based booting. Only\nomap3 is still using the legacy SRAM code, so we need to make it\nomap3 specific. Otherwise we can get errors like this on at least\ndm814x:\n\nUnhandled fault: imprecise external abort (0xc06) at 0xc08b156c\n...\n(omap_rev) from [<c08b12e0>] (omap_sram_init+0xf8/0x3e0)\n(omap_sram_init) from [<c08aca0c>] (omap_sdrc_init+0x10/0xb0)\n(omap_sdrc_init) from [<c08b581c>] (pdata_quirks_init+0x18/0x44)\n(pdata_quirks_init) from [<c08b5478>] (omap_generic_init+0x10/0x1c)\n(omap_generic_init) from [<c08a57e0>] (customize_machine+0x1c/0x40)\n(customize_machine) from [<c00098a4>] (do_one_initcall+0x80/0x1dc)\n(do_one_initcall) from [<c08a2ec4>] (kernel_init_freeable+0x218/0x2e8)\n(kernel_init_freeable) from [<c063a554>] (kernel_init+0x8/0xec)\n(kernel_init) from [<c000f890>] (ret_from_fork+0x14/0x24)\n\nLet's fix the issue by making sure omap_sdrc_init only gets called for\nomap3. To do that, we need to have compatible \"ti,omap3\" in the dts\nfiles. And let's also use \"ti,omap3630\" instead of \"ti,omap36xx\" like\nwe're supposed to.\n\nSigned-off-by: Tony Lindgren <tony@atomide.com>\n[d-gerlach@ti.com: Drop change to missing logicpd-torpedo-37xx-devkit]\nSigned-off-by: Dave Gerlach <d-gerlach@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/ecc64c5e3a0be3761da221da137197fd60834735"},{"sha":"ccc649744a38b6483d2c4e1496082c09fea8d069","author":{"email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com","name":"Grygorii Strashko"},"message":"ARM: OMAP4+: SMP: use lockless clkdm/pwrdm api in omap4_boot_secondary\n\ncommit 918af9f941af9995fcaa7ef1eb67c433a492e2b3  upstream\n\nOMAP CPU hotplug uses cpu1's clocks and power domains for CPU1 wake up\nfrom low power states (or turn on CPU1). This part of code is also\npart of system suspend (disable_nonboot_cpus()).\nFrom other side, cpu1's clocks and power domains are used by CPUIdle. All above\nfunctionality is mutually exclusive and, therefore, lockless clkdm/pwrdm api\ncan be used in omap4_boot_secondary().\n\nThis fixes below back-trace on -RT which is triggered by\npwrdm_lock/unlock():\n\nBUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917\n in_atomic(): 1, irqs_disabled(): 0, pid: 118, name: sh\n 9 locks held by sh/118:\n  #0:  (sb_writers#4){.+.+.+}, at: [<c0144a6c>] vfs_write+0x13c/0x164\n  #1:  (&of->mutex){+.+.+.}, at: [<c01b4c70>] kernfs_fop_write+0x48/0x19c\n  #2:  (s_active#24){.+.+.+}, at: [<c01b4c78>] kernfs_fop_write+0x50/0x19c\n  #3:  (device_hotplug_lock){+.+.+.}, at: [<c03cbff0>] lock_device_hotplug_sysfs+0xc/0x4c\n  #4:  (&dev->mutex){......}, at: [<c03cd284>] device_online+0x14/0x88\n  #5:  (cpu_add_remove_lock){+.+.+.}, at: [<c003af90>] cpu_up+0x50/0x1a0\n  #6:  (cpu_hotplug.lock){++++++}, at: [<c003ae48>] cpu_hotplug_begin+0x0/0xc4\n  #7:  (cpu_hotplug.lock#2){+.+.+.}, at: [<c003aec0>] cpu_hotplug_begin+0x78/0xc4\n  #8:  (boot_lock){+.+...}, at: [<c002b254>] omap4_boot_secondary+0x1c/0x178\n Preemption disabled at:[<  (null)>]   (null)\n\n CPU: 0 PID: 118 Comm: sh Not tainted 4.1.12-rt11-01998-gb4a62c3-dirty #137\n Hardware name: Generic DRA74X (Flattened Device Tree)\n [<c0017574>] (unwind_backtrace) from [<c0013be8>] (show_stack+0x10/0x14)\n [<c0013be8>] (show_stack) from [<c05a8670>] (dump_stack+0x80/0x94)\n [<c05a8670>] (dump_stack) from [<c05ad158>] (rt_spin_lock+0x24/0x54)\n [<c05ad158>] (rt_spin_lock) from [<c0030dac>] (clkdm_wakeup+0x10/0x2c)\n [<c0030dac>] (clkdm_wakeup) from [<c002b2c0>] (omap4_boot_secondary+0x88/0x178)\n [<c002b2c0>] (omap4_boot_secondary) from [<c0015d00>] (__cpu_up+0xc4/0x164)\n [<c0015d00>] (__cpu_up) from [<c003b09c>] (cpu_up+0x15c/0x1a0)\n [<c003b09c>] (cpu_up) from [<c03cd2d4>] (device_online+0x64/0x88)\n [<c03cd2d4>] (device_online) from [<c03cd360>] (online_store+0x68/0x74)\n [<c03cd360>] (online_store) from [<c01b4ce0>] (kernfs_fop_write+0xb8/0x19c)\n [<c01b4ce0>] (kernfs_fop_write) from [<c0144124>] (__vfs_write+0x20/0xd8)\n [<c0144124>] (__vfs_write) from [<c01449c0>] (vfs_write+0x90/0x164)\n [<c01449c0>] (vfs_write) from [<c01451e4>] (SyS_write+0x44/0x9c)\n [<c01451e4>] (SyS_write) from [<c0010240>] (ret_fast_syscall+0x0/0x54)\n CPU1: smp_ops.cpu_die() returned, trying to resuscitate\n\nCc: Tero Kristo <t-kristo@ti.com>\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/ccc649744a38b6483d2c4e1496082c09fea8d069"},{"sha":"b9811e894c9dbe62e64f26ab408070d00b633e73","author":{"email":"bd0da4b944f4f5c71572cb1afabf3c293f45b4c8@ti.com","name":"Keerthy"},"message":"gpio: davinci: Add the missing of-node pointer in the irq_domain_add_legacy function call\n\nCurrently the first parameter of irq_domain_add_legacy is NULL.\nirq_find_host function returns NULL when we do not populate the of_node\nand hence irq_of_parse_and_map call fails whenever we want to request a\ngpio irq. This fixes the request_irq failures for gpio interrupts.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b9811e894c9dbe62e64f26ab408070d00b633e73"},{"sha":"66a8f45b5e44072ba42624f96f06d23839ec06aa","author":{"email":"c1574519d727edaf2e16b260e452051ef77bf018@ti.com","name":"Lokesh Vutla"},"message":"gpio: davinci: Fix the number of controllers allocated\n\nDriver only needs to allocate for [ngpio / 32] controllers,\nas each controller handles 32 gpios. But the current driver\nallocates for ngpio of which the extra allocated are unused.\nFix it be registering only the required number of controllers.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\n[Ported to latest 4.1 platform branch from rfc]\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/66a8f45b5e44072ba42624f96f06d23839ec06aa"},{"sha":"ffc9414b3090115ca3053328097dc10d15259a24","author":{"email":"bd0da4b944f4f5c71572cb1afabf3c293f45b4c8@ti.com","name":"Keerthy"},"message":"gpio: davinci: Remove gpio2regs function to accommodate multi instances\n\ngpio2regs is written making an assumption that driver supports only\none instance of gpio controller. Removing this and adding a generic\narray so as to support multiple instances of gpio controllers.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/ffc9414b3090115ca3053328097dc10d15259a24"},{"sha":"b0ec434a7b064b9ed68ef72bf47cb8c803ce05e5","author":{"email":"c1574519d727edaf2e16b260e452051ef77bf018@ti.com","name":"Lokesh Vutla"},"message":"drivers: gpio: Add support for multiple IPs\n\nUpdate GPIO driver to support Multiple GPIO IPs.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/b0ec434a7b064b9ed68ef72bf47cb8c803ce05e5"},{"sha":"c16dea4649be8fe0bc6aa24a9c996171e954692a","author":{"email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com","name":"Grygorii Strashko"},"message":"gpio: davinci: irq support for multiple gpio controllers\n\nThe Davinci GPIO driver is implemented to work with one monolithic\nDavinci GPIO platform device which may have up to Y(144) gpios.\nThe Davinci GPIO driver instantiates number of GPIO chips with\nmax 32 gpio pins per each during initialization and one IRQ domain.\nSo, the current GPIO's  opjects structure is:\n\n<platform device> Davinci GPIO controller\n |- <gpio0_chip0> ------|\n ...                    |--- irq_domain (hwirq [0..143])\n |- <gpio0_chipN> ------|\n\nThe gpio2hwirq conversation is performing in the following way:\n hwirq = gpio0_chipX.base + gpio_offsetN\n\n where gpio_offsetN is gpio pin number inside gpio0_chipX\n and gpio0_chipX.base can have values 0..128 with step 32.\n\nAbove will work properly only when one Davinci GPIO controller is\npresent, but if second one (68 gpios) is added IRQs will not work for it,\nbecause gpio1_chipX.base will have values 144..208 with step 32 and\nabove formula will not work any more.\n\nHence, update Davinci GPIO driver to handle this situation properly:\n- add new field in struct davinci_gpio_controller.ctrl_base and\n  save Linux GPIO number of the first GPIO assigned to the Davinci GPIO\n  controller in .probe() - value of static variable \"bank_base\";\n- correct gpio2hwirq conversation formula as below\n  hwirq = (gpio0_chipX.base - gpio_controller.ctrl_base) + gpio_offsetN\n\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\n[j-keerthy@ti.com added the ctrl_base to keep track of gpios per controller]\nSigned-off-by: Keerthy <j-keerthy@ti.com>\nTested-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/c16dea4649be8fe0bc6aa24a9c996171e954692a"},{"sha":"12c7429515668a9b5ba8a29c7fb5e4f1a293b268","author":{"email":"bd0da4b944f4f5c71572cb1afabf3c293f45b4c8@ti.com","name":"Keerthy"},"message":"gpio: davinci: Store both irqs into the controller\n\nThere are 32 GPIOs per controller which means 2 banks with 16 gpios\nand 2 separate irqs. Hence store the both the irq numbers for the\ncontroller which makes it easier to distnguish the bank in irq handler.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/12c7429515668a9b5ba8a29c7fb5e4f1a293b268"},{"sha":"613d937359be730a18bade32c2d380daed619718","author":{"email":"bd0da4b944f4f5c71572cb1afabf3c293f45b4c8@ti.com","name":"Keerthy"},"message":"gpio: davinci: Add a separate compatible for k2g\n\nIn the case of k2g the clocks are handled differently as when compared\nwith other keystones. Hence adding a separate compatible and match tables\naccordingly.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/613d937359be730a18bade32c2d380daed619718"},{"sha":"5ea9e4b31235b39c61a84e5c022072d113d0327d","author":{"email":"bd0da4b944f4f5c71572cb1afabf3c293f45b4c8@ti.com","name":"Keerthy"},"message":"ARM: dts: k2g: Add gpio nodes\n\nk2g has 2 instances of gpio. The first one has all the 144 GPIOs\nfunctional( 9 banks with 16 gpios = 144). The second instance has\nonly the GPIO0:GPIO67 functional and rest are marked reserved.\n\nSigned-off-by: Keerthy <j-keerthy@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/5ea9e4b31235b39c61a84e5c022072d113d0327d"},{"sha":"6069a0f4e5f5860e6d064e191e09d8287b69344a","author":{"email":"94dddeeef08b001e003cce128ddc162a4e2c6cd2@ti.com","name":"Felipe Balbi"},"message":"ARM: 8434/2: Revert \"7655/1: smp_twd: make twd_local_timer_of_register() no-op for nosmp\"\n\ncommit 63c27ae7981e5c28abfe97ca5f6ef92a5070ce7a upstream\n\nThis reverts commit 904464b91eca8c665acea033489225af02eeb75a.\n\nThe problem pointed out by commit 904464b91eca (\"ARM: 7655/1:\nsmp_twd: make twd_local_timer_of_register() no-op for nosmp\")\ndoesn't exist anymore.\n\nWe can safely boot with nosmp and the warning won't show up.\n\nThe other side benefit of this patch is that TWD has a chance\nto probe on single-core A9 systems such as AM437x which sport\nTWD.\n\nWhile at that, also drop SMP dependency from TWD's Kconfig entry.\n\nCc: Shawn Guo <shawn.guo@linaro.org>\nCc: Dirk Behme <dirk.behme@de.bosch.com>\nAcked-by: Tony Lindgren <tony@atomide.com>\nSigned-off-by: Felipe Balbi <balbi@ti.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/6069a0f4e5f5860e6d064e191e09d8287b69344a"},{"sha":"90e7dde34bffc5ee0974560d373dcff3882952b8","author":{"email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com","name":"Grygorii Strashko"},"message":"clocksource/drivers/arm_global_timer: Fix suspend resume\n\ncommit 9c9ae5ffee2831c0b8c0b002443b093e141d08f1 upstream.\n\nNow the System stall is observed on TI AM437x based board (am437x-gp-evm)\nduring resuming from System suspend when ARM Global timer is selected as\nclocksource device (CPUIdle not enabled) - SysRq are working, but nothing\nelse.\n\nThe reason of stall is that ARM Global timer loses its contexts during\nSystem suspend:\n   GT_CONTROL.TIMER_ENABLE = 0 (unbanked)\n   GT_COUNTERx = 0\n\nHence, update ARM Global timer driver to reflect above behaviour\n- re-enable ARM Global timer on resume (GT_CONTROL.TIMER_ENABLE = 1)\n  if not enabled.\n\nCC: Arnd Bergmann <arnd@arndb.de>\nCc: John Stultz <john.stultz@linaro.org>\nCc: Felipe Balbi <balbi@ti.com>\nCc: Tony Lindgren <tony@atomide.com>\nCc: Marc Zyngier <marc.zyngier@arm.com>\nReviewed-by: Santosh Shilimkar <ssantosh@kernel.org>\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/90e7dde34bffc5ee0974560d373dcff3882952b8"},{"sha":"76118efa53fb89df1ea8eea0743c210a5f9ddf5e","author":{"email":"94dddeeef08b001e003cce128ddc162a4e2c6cd2@ti.com","name":"Felipe Balbi"},"message":"ARM: dts: am4372: add ARM timers and SCU nodes\n\ncommit 8cbd4c2f6a996f6cf5dfdf8775d331606cff95bd upstream.\n\nAM437x devices sport SCU, TWD and Global timers, let's add them to DTS\nso they have a chance to probe and be used by Linux.\n\nSigned-off-by: Felipe Balbi <balbi@ti.com>\nSigned-off-by: Tony Lindgren <tony@atomide.com>\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/76118efa53fb89df1ea8eea0743c210a5f9ddf5e"},{"sha":"0363ae14a9f8d78a08673b6341fac1da5201d660","author":{"email":"bfa0a1520768723a1c60e18250fb841c342eb8d8@ti.com","name":"Grygorii Strashko"},"message":"ARM: dts: am4372: fix clock source for arm twd and global timers\n\ncommit 14054fb1da099fd89208b8b319a00e0b902c7645 upstream.\n\nARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2.\nBut now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result.\nTimekeeping core misbehaves. For example, execution of command\n\"sleep 5\" will take 10 sec instead of 5.\n\nHence, fix it by adding mpu_periphclk (\"fixed-factor-clock\") and use\nit for clocking ARM TWD and Global timer (same way as on OMAP4).\n\nCc: Tony Lindgren <tony@atomide.com>\nCc: Felipe Balbi <balbi@ti.com>\nCc: Tero Kristo <t-kristo@ti.com>\nFixes:commit 8cbd4c2f6a99 (\"arm: boot: dts: am4372: add ARM timers and SCU nodes\")\nSigned-off-by: Grygorii Strashko <grygorii.strashko@ti.com>\nReviewed-by: Felipe Balbi <balbi@ti.com>\nSigned-off-by: Tony Lindgren <tony@atomide.com>","distinct":false,"url":"https://api.github.com/repos/RobertCNelson/ti-linux-kernel/commits/0363ae14a9f8d78a08673b6341fac1da5201d660"}]}