{"push_id":1122020327,"size":1,"distinct_size":0,"ref":"refs/heads/master","head":"d7697eb14a0195cc3726bf45fdf38c631b6f6507","before":"a26a0ad4504e99182e3548db8f407c3dad7302b0","commits":[{"sha":"d7697eb14a0195cc3726bf45fdf38c631b6f6507","author":{"email":"932f30a41a696f6a414c4f83dfffd299d2402155@eecs.berkeley.edu","name":"jackkoenig"},"message":"Update BackendCompilationUtilities.verilogToCpp to specify top-module\n\nThis prevents Verilator from erroring when it cannot determine the top-module.\nIt also changes the PRINTF_COND guard to correctly use the top-level reset\ninstead of just the top of the Chisel-generated code.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/d7697eb14a0195cc3726bf45fdf38c631b6f6507"}]}
{"actor":{"display_login":"jackkoenig"}}