{"push_id":1211856776,"size":13,"distinct_size":13,"ref":"refs/heads/rtems-rpi-devel","head":"011006d7f26d6d195f7523760bddde2e36364901","before":"eb6c3e507088d644d9173a1ebb835f5210b2fc72","commits":[{"sha":"55bde66ff84646f00a5ca5816f22aa13405679ed","author":{"name":"Punit Vara","email":"f1bfd160f7063ecf85d840bada3131b0f2dbc21d@gmail.com"},"message":"beagle: pwm polishing\n\n\t. added a README to pwm\n\t. added select_pwmss() to select pwmss-generic registers, as opposed\n\t  to PWM-specific registers\n\t. added pwmss_clock_en_status(), beagle_pwmss_is_running() and pwmss_tb_clock_check()\n\t. other API improvements\n\t. style improvements","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/55bde66ff84646f00a5ca5816f22aa13405679ed"},{"sha":"8d785f72d9610fb80a65d7848404f0f7507e026c","author":{"name":"Sebastian Huber","email":"ad858f69eb0c2747f96a84a1ee9b28ef8326022d@embedded-brains.de"},"message":"bsps/powerpc: Fix AtliVec context switch\n\nProperly pass the stack aligned context to _CPU_Context_switch_altivec()\nsince _CPU_altivec_ctxt_off defined via ppc_context.\n\nClose #2761.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/8d785f72d9610fb80a65d7848404f0f7507e026c"},{"sha":"c2a4b8bf37de516468cf73e039f0d4b1b4921d84","author":{"name":"Sebastian Huber","email":"ad858f69eb0c2747f96a84a1ee9b28ef8326022d@embedded-brains.de"},"message":"bsps/powerpc: Fix shared console driver\n\nThe Termios modes are now an emum.  Do not use them in #if expressions.\n\nClose #2762.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/c2a4b8bf37de516468cf73e039f0d4b1b4921d84"},{"sha":"a48c05226d8ca89ba11483e75dad74d373af27e8","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"arm/raspberrypi: cache manager can be used for mailbox synchronization now. Remove workarounds.\n\nSigned-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/a48c05226d8ca89ba11483e75dad74d373af27e8"},{"sha":"3338121832ab0fef34c1295f7328122a293ae850","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"bsps/arm: do not disable MMU during translation table management operations.\n\nDisabling MMU requires complex cache flushing and invalidation\noperations. There is almost no way how to do that right\non SMP system without stopping all other CPUs. On the other hand,\nthere is documented sequence of operations which should be used\naccording to ARM manual and it guarantees even distribution\nof maintenance operations to other cores for last generation\nof Cortex-A cores with multiprocessor extension.\n\nThis change could require addition of appropriate entry\nto arm_cp15_start_mmu_config_table for some BSPs to ensure\nthat MMU table stays accessible after MMU is enabled\n\n  {\n    .begin = (uint32_t) bsp_translation_table_base,\n    .end = (uint32_t) bsp_translation_table_base + 0x4000,\n    .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED\n  }","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/3338121832ab0fef34c1295f7328122a293ae850"},{"sha":"577e7fb337c8de90d0b5661ef5b901042817366d","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"arm/bsps: CP15 and basic cache support entire cache clean for more architecture variants now.\n\nNext cache operations should work on most of cores now\n\n  rtems_cache_flush_entire_data()\n  rtems_cache_invalidate_entire_data()\n  rtems_cache_invalidate_entire_instruction()\n\nInstruction cache invalidate works on the first level for now only.\nData cacache operations are extended to ensure flush/invalidate\non all cache levels.\n\nThe CP15 arm_cp15_data_cache_clean_all_levels() function extended\nto continue through unified levels too (ctype = 4).","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/577e7fb337c8de90d0b5661ef5b901042817366d"},{"sha":"bef2b737a2361f4050ed80f30e5087ed5543407f","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"arm/raspberrypi: use cache manager operations to flush/invalidate all cache levels.\n\nThis fix strange behavior where some stale content has been\nstored in level 2 cache before RTEMS has been start from U-boot\nwhich has reappeared after MMU enable and shadow vector\ntable at start of SDRAM.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/bef2b737a2361f4050ed80f30e5087ed5543407f"},{"sha":"dcf806ef51f1b6893e47d19a5d36becde4df9273","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"arm/raspberrypi: reorder and update MMU config table to nor force RW section later to RO.\n\nEnable even the first megabyte of SDRAM to be cache-able after\nproblems with stale cache content has been resolved by previous commit.\nBecause major part of application usually fits to the first\nmegabyte this speedups test dhrystone application by factor 40.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/dcf806ef51f1b6893e47d19a5d36becde4df9273"},{"sha":"8f0cb3ddb4f4535215ab01133366bc5e57bd20fa","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"libdl/rtl-obj.c: synchronize cache after code relocation.\n\nMemory content changes caused by relocation has to be\npropagated to memory/cache level which is used/snooped\nduring instruction cache fill.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/8f0cb3ddb4f4535215ab01133366bc5e57bd20fa"},{"sha":"fa4eef1501cc933c15a4dec295ed8cf6db89fa1e","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"HACKING use ticker for experiments and debugging of ARM and Raspberry Pi.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/fa4eef1501cc933c15a4dec295ed8cf6db89fa1e"},{"sha":"697bf5451d5b0fb5caf55098464425b6e60457e9","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"HACKING Raspberry Pi BSP startup debugging and HYP experiments.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/697bf5451d5b0fb5caf55098464425b6e60457e9"},{"sha":"31768bb3386b5fbef08b1efad539fae015d522f7","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"HACKING force command line to switch to graphic console if monitor is present.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/31768bb3386b5fbef08b1efad539fae015d522f7"},{"sha":"011006d7f26d6d195f7523760bddde2e36364901","author":{"name":"Pavel Pisa","email":"dc6fc85b5f2965e5f837e3b11f152db18052dfcd@cmp.felk.cvut.cz"},"message":"HACKING random VideoCore and cache debug and experiments.","distinct":true,"url":"https://api.github.com/repos/ppisa/rtems/commits/011006d7f26d6d195f7523760bddde2e36364901"}]}
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