{"push_id":1465064438,"size":5,"distinct_size":5,"ref":"refs/heads/staging","head":"d6ac8e22c7c5525db1da79fd1d1f03ee6b557f0d","before":"157db407533fb55c0ce0c133991e3cb951b76484","commits":[{"sha":"bfe67e80b2dabb29e0b40d89d91023f0d75934be","author":{"name":"Jan Beulich","email":"ae7900a0c785918fc3eaa9d1a92a76bc4e651ece@suse.com"},"message":"x86emul: check for CMPXCHG8B availability\n\nWe can't exclude someone wanting to hide the instruction from guests.\n\nSigned-off-by: Jan Beulich <jbeulich@suse.com>\nReviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/bfe67e80b2dabb29e0b40d89d91023f0d75934be"},{"sha":"1cb650c3191f8b85defb4d2ab6f183fa2926e494","author":{"name":"Haozhong Zhang","email":"ae5a5091cec64993dcc13419e996447dfccaf8cc@intel.com"},"message":"vvmx: fix the wrong address width in c/s 08fac63\n\nc/s 08fac63 misused v->domain-arch.paging.gfn_bits as the width of\nguest physical address and missed adding PAGE_SHIFT to it when\nchecking vmxon operand.\n\nSigned-off-by: Haozhong Zhang <haozhong.zhang@intel.com>\nReviewed-by: Jan Beulich <jbeulich@suse.com>\nAcked-by: Kevin Tian <kevin.tian@intel.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/1cb650c3191f8b85defb4d2ab6f183fa2926e494"},{"sha":"44d3196903f3ae5ac3d27da626107131e3e35603","author":{"name":"Haozhong Zhang","email":"ae5a5091cec64993dcc13419e996447dfccaf8cc@intel.com"},"message":"vvmx: replace vmreturn() by vmsucceed() and vmfail*()\n\nReplace vmreturn() by vmsucceed(), vmfail(), vmfail_valid() and\nvmfail_invalid(), which are consistent to the pseudo code on Intel\nSDM, and allow to return VM instruction error numbers to L1\nhypervisor.\n\nSigned-off-by: Haozhong Zhang <haozhong.zhang@intel.com>\nAcked-by: Andrew Cooper <andrew.cooper3@citrix.com>\nAcked-by: Kevin Tian <kevin.tian@intel.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/44d3196903f3ae5ac3d27da626107131e3e35603"},{"sha":"19fb14622e94185afd34081e3bc74e9c1663e781","author":{"name":"Boris Ostrovsky","email":"8d8eed10c3f35eaa3a548daad1882614e248ed99@oracle.com"},"message":"x86/pmtimer: move ACPI registers from PMTState to hvm_domain\n\nThese registers (pm1a specifically) are not all specific to pm timer\nand are accessed by non-pmtimer code (for example, sleep/power button\nemulation).\n\nThe public name for save state structure is kept as 'pmtimer' to avoid\ncode churn with the expected changes in migration code. hvm_hw_acpi\nname is introduced for internal use but when migration code is updated\nhvm_hw_pmtimer will be renamed to hvm_hw_acpi.\n\nNo functional changes are introduced.\n\n(While this file is being modified, also add emacs mode style rune)\n\nSigned-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>\nReviewed-by: Jan Beulich <jbeulich@suse.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/19fb14622e94185afd34081e3bc74e9c1663e781"},{"sha":"d6ac8e22c7c5525db1da79fd1d1f03ee6b557f0d","author":{"name":"Boris Ostrovsky","email":"8d8eed10c3f35eaa3a548daad1882614e248ed99@oracle.com"},"message":"acpi/x86: define ACPI IO registers for PVH guests\n\nDefine VCPU available map address (used by AML's PRSC method)\nand GPE0 CPU hotplug event number. Use these definitions in mk_dsdt\ninstead hardcoded values.\n\nThese definitions will later be used by both the hypervisor and\nthe toolstack (initially for PVH guests only), thus they are\nplaced in public headers.\n\nSigned-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>\nReviewed-by: Jan Beulich <jbeulich@suse.com>","distinct":true,"url":"https://api.github.com/repos/mirage/xen/commits/d6ac8e22c7c5525db1da79fd1d1f03ee6b557f0d"}]}
{"actor":{"display_login":"avsm"}}