{"push_id":1123086793,"size":216,"distinct_size":1,"ref":"refs/heads/work/hns/iio/palmas/bindings-v2","head":"6c438ef51aab7eaa5da53841f7b699ecff7d8789","before":"4493749eb061969745007295a10eadf10561ab48","commits":[{"sha":"6ad3122a08e3a9c2148873665752e87cf4f393cc","author":{"email":"66deb1d63f85161cc287ce2bac0c65cb5ae958a7@secunet.com","name":"Steffen Klassert"},"message":"flowcache: Avoid OOM condition under preasure\n\nWe can hit an OOM condition if we are under presure because\nwe can not free the entries in gc_list fast enough. So add\na counter for the not yet freed entries in the gc_list and\nrefuse new allocations if the value is too high.\n\nSigned-off-by: Steffen Klassert <steffen.klassert@secunet.com>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/6ad3122a08e3a9c2148873665752e87cf4f393cc"},{"sha":"215276c0147ef49bc07692ca68bae35a30a64b9a","author":{"email":"66deb1d63f85161cc287ce2bac0c65cb5ae958a7@secunet.com","name":"Steffen Klassert"},"message":"xfrm: Reset encapsulation field of the skb before transformation\n\nThe inner headers are invalid after a xfrm transformation.\nSo reset the skb encapsulation field to ensure nobody tries\nto access the inner headers.\n\nSigned-off-by: Steffen Klassert <steffen.klassert@secunet.com>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/215276c0147ef49bc07692ca68bae35a30a64b9a"},{"sha":"8d48794bb3bf7d7e421204a8cc3bd5c95ffc609b","author":{"email":"3bfd69b8c2014438b0dfada1b30090ecff710124@intel.com","name":"Mihai Mihalache"},"message":"regulator: gpio: check return value of of_get_named_gpio\n\nAt boot time the regulator driver can be initialized before the\ngpio, in which case the call to of_get_named_gpio will return\nEPROBE_DEFER. This value is silently passed to regulator_register\nwhich will return success, although the gpio is not registered\n(regulator_ena_gpio_request not called) as the value passed is\ndetected as invalid. The gpio_regulator_probe will therefore\nsucceed win no gpio requested.\n\nSigned-off-by: Mihai Mihalache <mihai.d.mihalache@intel.com>\nReviewed-by: Hans Holmberg <hans.holmberg@intel.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/8d48794bb3bf7d7e421204a8cc3bd5c95ffc609b"},{"sha":"2596e07a3ed5a5f4d8b89be316c2b704d6f5dc5f","author":{"email":"f2c659f01951776204a6c5b902787d9019fbeebd@arndb.de","name":"Arnd Bergmann"},"message":"regmap: fix documentation to match code\n\nThe regmap binding talks about one thing, which is register\nendianess, and it gets almost every aspect of it wrong.\n\nThis replaces the current text of the file with a version\nthat makes more sense and that matches what we implement\nnow.\n\nSigned-off-by: Arnd Bergmann <arnd@arndb.de>\nFixes: a06c488da0b0 (\"regmap: Add explict native endian flag to DT bindings\")\nFixes: 275876e208e2 (\"regmap: Add the DT binding documentation for endianness\")\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/2596e07a3ed5a5f4d8b89be316c2b704d6f5dc5f"},{"sha":"9f9f8b863ad130ec0c25f378bdbad64ba71291de","author":{"email":"b51b9a92386687a9ac927cebfa0f978adeb8cea5@kernel.org","name":"Mark Brown"},"message":"regmap: mmio: Fix value endianness selection\n\nCurrently when selecting value endianness we check the register\nendiannes, not the value endianness.\n\nReported-by: Alexander Stein <alexander.stein@systec-electronic.com>\nTested-by: Alexander Stein <alexander.stein@systec-electronic.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/9f9f8b863ad130ec0c25f378bdbad64ba71291de"},{"sha":"3b672623079bb3e5685b8549e514f2dfaa564406","author":{"email":"1a8531307367602b8284517edb33d53d54e5ce8e@samsung.com","name":"Krzysztof Kozlowski"},"message":"regulator: s2mps11: Fix invalid selector mask and voltages for buck9\n\nThe buck9 regulator of S2MPS11 PMIC had incorrect vsel_mask (0xff\ninstead of 0x1f) thus reading entire register as buck9's voltage. This\neffectively caused regulator core to interpret values as higher voltages\nthan they were and then to set real voltage much lower than intended.\n\nThe buck9 provides power to other regulators, including LDO13\nand LDO19 which supply the MMC2 (SD card). On Odroid XU3/XU4 the lower\nvoltage caused SD card detection errors on Odroid XU3/XU4:\n\tmmc1: card never left busy state\n\tmmc1: error -110 whilst initialising SD card\n\nDuring driver probe the regulator core was checking whether initial\nvoltage matches the constraints. With incorrect vsel_mask of 0xff and\ndefault value of 0x50, the core interpreted this as 5 V which is outside\nof constraints (3-3.775 V). Then the regulator core was adjusting the\nvoltage to match the constraints. With incorrect vsel_mask this new\nvoltage mapped to a vere low voltage in the driver.\n\nSigned-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>\nReviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>\nTested-by: Javier Martinez Canillas <javier@osg.samsung.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>\nCc: <stable@vger.kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/3b672623079bb3e5685b8549e514f2dfaa564406"},{"sha":"4f7d6dd4df8b388e2056c89b528254cdd79dea2a","author":{"email":"b51b9a92386687a9ac927cebfa0f978adeb8cea5@kernel.org","name":"Mark Brown"},"message":"regmap: Fix implicit inclusion of device.h\n\ninternal.h is using dev_name() but doesn't include device.h which\ndefines it.  Add an explicit include to avoid build problems due to\nthis.\n\nTested-by: Alexander Stein <alexander.stein@systec-electronic.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/4f7d6dd4df8b388e2056c89b528254cdd79dea2a"},{"sha":"0dbdb76c0ca8e7caf27c9a210f64c4359e2974a4","author":{"email":"b51b9a92386687a9ac927cebfa0f978adeb8cea5@kernel.org","name":"Mark Brown"},"message":"regmap: mmio: Parse endianness definitions from DT\n\nSince we changed to do formatting in the bus we now skip all the format\nparsing that the core does for its data marshalling code.  This means\nthat we skip the DT parsing it does which breaks some systems, we need\nto add an explict call in the MMIO code to do this.\n\nReported-by: Alexander Stein <alexander.stein@systec-electronic.com>\nTested-by: Alexander Stein <alexander.stein@systec-electronic.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/0dbdb76c0ca8e7caf27c9a210f64c4359e2974a4"},{"sha":"d6af1a31cc72fbd558c7eddbc36f61bf09d1cf6a","author":{"email":"66deb1d63f85161cc287ce2bac0c65cb5ae958a7@secunet.com","name":"Steffen Klassert"},"message":"vti: Add pmtu handling to vti_xmit.\n\nWe currently rely on the PMTU discovery of xfrm.\nHowever if a packet is locally sent, the PMTU mechanism\nof xfrm tries to do local socket notification what\nmight not work for applications like ping that don't\ncheck for this. So add pmtu handling to vti_xmit to\nreport MTU changes immediately.\n\nReported-by: Mark McKinstry <Mark.McKinstry@alliedtelesis.co.nz>\nSigned-off-by: Steffen Klassert <steffen.klassert@secunet.com>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/d6af1a31cc72fbd558c7eddbc36f61bf09d1cf6a"},{"sha":"2ed94f6fde066fb37bc3553b786edb805561699e","author":{"email":"b51b9a92386687a9ac927cebfa0f978adeb8cea5@kernel.org","name":"Mark Brown"},"message":"regmap: mmio: Explicitly say little endian is the defualt in the bus config\n\nOtherwise the DT parsing will default to big endian if nothing is\nspecified.\n\nReported-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/2ed94f6fde066fb37bc3553b786edb805561699e"},{"sha":"03cc0789a690eb9ab07070376252961caeae7441","author":{"email":"de609eb4d5d70b1d38ec6642adbfc33a2781f63c@zeniv.linux.org.uk","name":"Al Viro"},"message":"do_splice_to(): cap the size before passing to ->splice_read()\n\npipe capacity won't exceed 2G anyway.\n\nSigned-off-by: Al Viro <viro@zeniv.linux.org.uk>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/03cc0789a690eb9ab07070376252961caeae7441"},{"sha":"92dc20d83adec565378254c0630e839ff5674e14","author":{"email":"6f555c040af13451131a2610fd25bef517f71472@cogentembedded.com","name":"Andrey Vostrikov"},"message":"spi: spi-fsl-dspi: Fix cs_change handling in message transfer\n\nThere are use cases when chip select should be triggered between transfers\nin single SPI message. Current implementation does this only on last\ntransfer in message ignoring cs_change value provided in current transfer.\n\nSigned-off-by: Andrey Vostrikov <andrey.vostrikov@cogentembedded.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/92dc20d83adec565378254c0630e839ff5674e14"},{"sha":"357f435d8a0d32068c75f3c7176434d992b3adb7","author":{"email":"de609eb4d5d70b1d38ec6642adbfc33a2781f63c@zeniv.linux.org.uk","name":"Al Viro"},"message":"fix the copy vs. map logics in blk_rq_map_user_iov()\n\nSigned-off-by: Al Viro <viro@zeniv.linux.org.uk>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/357f435d8a0d32068c75f3c7176434d992b3adb7"},{"sha":"8070954d7c9fffa527e785292e901867338f79a9","author":{"email":"3807cf899f217da549814bf6c330d3b6e6819ccf@gmail.com","name":"Akinobu Mita"},"message":"spi: omap2-mcspi: Undo broken fix for dma transfer of vmalloced buffer\n\nThis reverts commit 3525e0aac91c4de5d20b1f22a6c6e2b39db3cc96.\n\nThe DMA transfer for RX buffer was not handled correctly in this change.\n\nThe actual transfer length for DMA RX can be less than xfer->len in the\nspecific condition and the last words will be filled after the DMA\ncompletion, but the commit doesn't consider it and the dmaengine is\nstarted with rx_sg mapped by spi core.\n\nThe solution for this at least requires more lines than this commit\nhas inserted.  So revert it for now.\n\nSigned-off-by: Akinobu Mita <akinobu.mita@gmail.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/8070954d7c9fffa527e785292e901867338f79a9"},{"sha":"ea1b60fb085839a9544cb3a0069992991beabb7f","author":{"email":"a9aff6bdb06df0f1e86a184e2c263c6782eaee6c@codethink.co.uk","name":"Ben Hutchings"},"message":"spi: spi-ti-qspi: Fix FLEN and WLEN settings if bits_per_word is overridden\n\nEach transfer can specify 8, 16 or 32 bits per word independently of\nthe default for the device being addressed.  However, currently we\ncalculate the number of words in the frame assuming that the word size\nis the device default.\n\nIf multiple transfers in the same message have differing\nbits_per_word, we bitwise-or the different values in the WLEN register\nfield.\n\nFix both of these.  Also rename 'frame_length' to 'frame_len_words' to\nmake clear that it's not a byte count like spi_message::frame_length.\n\nSigned-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>\nSigned-off-by: Mark Brown <broonie@kernel.org>\nCc: stable@vger.kernel.org","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/ea1b60fb085839a9544cb3a0069992991beabb7f"},{"sha":"1ff7760ff66b98ef244bf0e5e2bd5310651205ad","author":{"email":"a9aff6bdb06df0f1e86a184e2c263c6782eaee6c@codethink.co.uk","name":"Ben Hutchings"},"message":"spi: spi-ti-qspi: Handle truncated frames properly\n\nWe clamp frame_len_words to a maximum of 4096, but do not actually\nlimit the number of words written or read through the DATA registers\nor the length added to spi_message::actual_length.  This results in\nsilent data corruption for commands longer than this maximum.\n\nRecalculate the length of each transfer, taking frame_len_words into\naccount.  Use this length in qspi_{read,write}_msg(), and to increment\nspi_message::actual_length.\n\nSigned-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>\nSigned-off-by: Mark Brown <broonie@kernel.org>\nCc: stable@vger.kernel.org","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/1ff7760ff66b98ef244bf0e5e2bd5310651205ad"},{"sha":"dec8e8f6e6504aa3496c0f7cc10c756bb0e10f44","author":{"email":"cbd79eb9617449d4bb49d0087b0eb70c6cf062b0@codeaurora.org","name":"Jack Pham"},"message":"regmap: spmi: Fix regmap_spmi_ext_read in multi-byte case\n\nSpecifically for the case of reads that use the Extended Register\nRead Long command, a multi-byte read operation is broken up into\n8-byte chunks.  However the call to spmi_ext_register_readl() is\nincorrectly passing 'val_size', which if greater than 8 will\nalways fail.  The argument should instead be 'len'.\n\nFixes: c9afbb05a9ff (\"regmap: spmi: support base and extended register spaces\")\nSigned-off-by: Jack Pham <jackp@codeaurora.org>\nSigned-off-by: Mark Brown <broonie@kernel.org>\nCc: stable@vger.kernel.org","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/dec8e8f6e6504aa3496c0f7cc10c756bb0e10f44"},{"sha":"66ec246eb9982e7eb8e15e1fc55f543230310dd0","author":{"email":"ed47dfa4cd43d03d92ccc66ffdb9609c96fcf22b@linux.intel.com","name":"Jarkko Nikula"},"message":"spi: pxa2xx: Do not detect number of enabled chip selects on Intel SPT\n\nCertain Intel Sunrisepoint PCH variants report zero chip selects in SPI\ncapabilities register even they have one per port. Detection in\npxa2xx_spi_probe() sets master->num_chipselect to 0 leading to -EINVAL\nfrom spi_register_master() where chip select count is validated.\n\nFix this by not using SPI capabilities register on Sunrisepoint. They don't\nhave more than one chip select so use the default value 1 instead of\ndetection.\n\nFixes: 8b136baa5892 (\"spi: pxa2xx: Detect number of enabled Intel LPSS SPI chip select signals\")\nSigned-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>\nSigned-off-by: Mark Brown <broonie@kernel.org>\nCc: stable@vger.kernel.org","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/66ec246eb9982e7eb8e15e1fc55f543230310dd0"},{"sha":"8d4d5c3a7c25e69075e60e5e70c1e05c205aef89","author":{"email":"2d324f4ca95610bde432fa2af2f28cd21110687d@free-electrons.com","name":"Maxime Ripard"},"message":"regulator: axp20x: Fix LDO4 linear voltage range\n\nThe current linear voltage range for the LDO4 regulator found in the APX20X\nPMICs assumes that the voltage is linear between 2.5 and 3.1V.\n\nHowever, the PMIC can output up to 3.3V on that regulator by skipping the\n2.6V and 2.9V steps.\n\nFix the ranges to read and set the proper voltages.\n\nFixes: 13d57e64352a (\"regulator: axp20x: Use linear voltage ranges for AXP20X LDO4\")\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>\nAcked-by: Chen-Yu Tsai <wens@csie.org>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/8d4d5c3a7c25e69075e60e5e70c1e05c205aef89"},{"sha":"a2262e5a12e05389ab4c7fc5cf60016b041dd8dc","author":{"email":"9fa1be1a5b5729e4c6b404f34c9ce49ff4882fd8@redhat.com","name":"Hans de Goede"},"message":"regulator: axp20x: Fix axp22x ldo_io voltage ranges\n\nThe minium voltage of 1800mV is a copy and paste error from the axp20x\nregulator info. The correct minimum voltage for the ldo_io regulators\non the axp22x is 700mV.\n\nFixes: 1b82b4e4f954 (\"regulator: axp20x: Add support for AXP22X regulators\")\nSigned-off-by: Hans de Goede <hdegoede@redhat.com>\nAcked-by: Chen-Yu Tsai <wens@csie.org>\nSigned-off-by: Mark Brown <broonie@kernel.org>","distinct":false,"url":"https://api.github.com/repos/goldelico/gta04-kernel/commits/a2262e5a12e05389ab4c7fc5cf60016b041dd8dc"}]}
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