{"push_id":1419374155,"size":62,"distinct_size":1,"ref":"refs/heads/chisel2sanitychecks","head":"3ee2d6769842866cf8e5969aa68f874b4f364e16","before":"c79811fcd7a326cf419fd5813f3fec4a9789fa28","commits":[{"sha":"aea7e1e754a3ebdb5b7e84c3ae1d35b16e547823","author":{"name":"Donggyu Kim","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"create SeqMems' read ports inside when statement\n\nthis helps firrtl to infer read enable signals","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/aea7e1e754a3ebdb5b7e84c3ae1d35b16e547823"},{"sha":"5272db0bc2ab5a1653168906c636b9099a96348b","author":{"name":"Andrew Waterman","email":"3251a4cbcb3b67580115a94658be701d1d6a2de6@eecs.berkeley.edu"},"message":"Refactor and fix field reflection (#342)\n\nNo more need for e.g.\r\n\r\n    new Bundle {\r\n      def foo(dummy: Int): Data\r\n    }\r\n\r\nas now you can write\r\n\r\n    new Bundle {\r\n      def foo: Data\r\n    }\r\n\r\nThis also removes code duplication with Module.\r\n\r\nh/t @sdtwigg","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/5272db0bc2ab5a1653168906c636b9099a96348b"},{"sha":"72d3290ab5c536fef689da1ea719b2876440eadd","author":{"name":"Jim Lawson","email":"c2ddf9772b1cc315a7df3172997ed349def67758@berkeley.edu"},"message":"Existence of unmanaged firrtl.jar, replaces sbt managed dependency.\nSince chisel now depends on firrtl, we need a way for super projects (i.e., rocket-chip) to control the actual firrtl package used by chisel.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/72d3290ab5c536fef689da1ea719b2876440eadd"},{"sha":"bf83e428bfc4cbdecf86e464fc343bb6a030bdaa","author":{"name":"Jim Lawson","email":"c2ddf9772b1cc315a7df3172997ed349def67758@berkeley.edu"},"message":"Use unmanagedClasspath and allDependencies to determine firrtl dependency.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/bf83e428bfc4cbdecf86e464fc343bb6a030bdaa"},{"sha":"4d684398a1774a8b6a7a86e9d2dd92a165e02cfe","author":{"name":"Donggyu","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"Merge pull request #339 from ucb-bar/fix_seqmem_enable\n\nfix SeqMem's read port creation","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/4d684398a1774a8b6a7a86e9d2dd92a165e02cfe"},{"sha":"09282f32bec847bcd0b652f778f42be13c7d027e","author":{"name":"Andrew Waterman","email":"3251a4cbcb3b67580115a94658be701d1d6a2de6@cs.berkeley.edu"},"message":"Preserve legacy cloneType behavior in compatibility mode\n\nf1507aa7cec86ca8f5de13ddc96fd046370dfe1d triggers a rocket-chip\nregression, because Chisel used to not preserve flippedness on\ncloneType.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/09282f32bec847bcd0b652f778f42be13c7d027e"},{"sha":"224ee397db324067b35874bf22c76a63e9ca531b","author":{"name":"Andrew Waterman","email":"3251a4cbcb3b67580115a94658be701d1d6a2de6@cs.berkeley.edu"},"message":"Plug holes where defaultCompileOptions leaked in\n\ndefaultCompileOptions is convenient, but it frequently foils the\ncompatibility layer by providing strict defaults rather than passing\nthrough the user's CompileOptions.  This notably manifests for\nchiselCloneType, which has different behavior for chisel3 and Chisel.\n\nIdeally, we'd get rid of defaultCompileOptions within chisel3.core\nand only supply it to people who import chisel3._ (attn. @ucbjrl).\nThat would statically prevent further regressions of this nature\nwithin the core.\n\nThe change to Vec.truncateIndex seems extraneous, but I chose an\nalternate implementation rather than requiring compileOptions in\nanother place.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/224ee397db324067b35874bf22c76a63e9ca531b"},{"sha":"0a8c369f388bac326bfe8a598aaf6d8fa13e6dfa","author":{"name":"Andrew Waterman","email":"3251a4cbcb3b67580115a94658be701d1d6a2de6@cs.berkeley.edu"},"message":"Add firrtl.jar to .gitignore","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/0a8c369f388bac326bfe8a598aaf6d8fa13e6dfa"},{"sha":"153ef841e4bd76113736202460de906b4af1138a","author":{"name":"Jim Lawson","email":"c2ddf9772b1cc315a7df3172997ed349def67758@berkeley.edu"},"message":"Update \"alpha\" references to \"beta\".","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/153ef841e4bd76113736202460de906b4af1138a"},{"sha":"30b0d0e2b7e104dd16102f17a03d25fdb3ba617a","author":{"name":"Adam Izraelevitz","email":"be54013606a403c854c87d076d7f638d04be7db1@gmail.com"},"message":"Changed T to _T for generated names (#349)\n\nPrefix temporary names with underscores so Verilator won't trace them\r\nUse verilator argument \"--trace-underscore\" if you want to trace these\r\nsignals","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/30b0d0e2b7e104dd16102f17a03d25fdb3ba617a"},{"sha":"891c73d8819b6bd117b96ce3c77c72df023d3a4c","author":{"name":"Jim Lawson","email":"c2ddf9772b1cc315a7df3172997ed349def67758@berkeley.edu"},"message":"Move migration info to wiki.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/891c73d8819b6bd117b96ce3c77c72df023d3a4c"},{"sha":"b2b80ce24881782b82b545e0e3cb2a0e4ef83557","author":{"name":"Jim Lawson","email":"c2ddf9772b1cc315a7df3172997ed349def67758@berkeley.edu"},"message":"Update Getting Started, Tutorial, and Project Setup sections.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/b2b80ce24881782b82b545e0e3cb2a0e4ef83557"},{"sha":"e60761cf72ba572da0bb8387a4506f5c3e211ac9","author":{"name":"Jack","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Add SourceInfo.makeMessage to better use SourceInfo in error messages","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/e60761cf72ba572da0bb8387a4506f5c3e211ac9"},{"sha":"815b1c3cb311b7f4dfb7a2f00e0e2d62795bdc6b","author":{"name":"Jack","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Add checks for misuse or omission of Module()\n\nImplemented by adding a Boolean to check for alternating invocations of object\nModule.apply and the constructor of abstract class Module.\nFixes #192","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/815b1c3cb311b7f4dfb7a2f00e0e2d62795bdc6b"},{"sha":"29f84617ea30c7dd30c9616bcdb9a1894b8a0762","author":{"name":"ducky","email":"fcb2fe81613883fb10b15eab0f14f45c69bd1cd9@berkeley.edu"},"message":"Eliminate some doc warnings","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/29f84617ea30c7dd30c9616bcdb9a1894b8a0762"},{"sha":"e4ff95a6beec01d437ac0ba289549641e3bb9bae","author":{"name":"Richard Lin","email":"3ca08056248fd8f3a34cc4a2cd8c2b1914420e3a@gmail.com"},"message":"Merge pull request #374 from ucb-bar/docgix\n\nEliminate some doc warnings","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/e4ff95a6beec01d437ac0ba289549641e3bb9bae"},{"sha":"b2afa964431c9f109cf10c83d5db49a8d5799b58","author":{"name":"Stevo","email":"cd7fe8c2f4e0c80002bbf336aba9b9a0e667a8ed@berkeley.edu"},"message":"Shift register enable gates all stages, not just first\n\nAlso, remove no-longer-special case for n=1.","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/b2afa964431c9f109cf10c83d5db49a8d5799b58"},{"sha":"6929ca0fc64b562f4852a49df617a1836e083563","author":{"name":"jackkoenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@eecs.berkeley.edu"},"message":"Change Verilator invocation to use O1\n\nWorkaround for:\nhttp://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/6929ca0fc64b562f4852a49df617a1836e083563"},{"sha":"822160cc8e76e70643fb56707bb39f6f7526b6fd","author":{"name":"jackkoenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@eecs.berkeley.edu"},"message":"Add support for parameterized BlackBoxes\n\nAlso restrict black boxes to not allow hardware inside of them since it was\nbeing silently dropped anyway.\n\nResolves #289","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/822160cc8e76e70643fb56707bb39f6f7526b6fd"},{"sha":"667a26bddb6133e8b243061f8a5fc5fe586cc1ae","author":{"name":"ducky","email":"fcb2fe81613883fb10b15eab0f14f45c69bd1cd9@berkeley.edu"},"message":"Range macro initial impl","distinct":false,"url":"https://api.github.com/repos/ucb-bar/chisel3/commits/667a26bddb6133e8b243061f8a5fc5fe586cc1ae"}]}
{"actor":{"display_login":"ucbjrl"}}