{"push_id":1298847500,"size":2,"distinct_size":1,"ref":"refs/heads/eos3.0","head":"288612e282c8383be159f9c3ffaf19b640236fc1","before":"e9d22daeece57f24e9d5f0c6f1ee4b1e1ea64f4e","commits":[{"sha":"c19792028cb5cd9ce34a0e506793ec98e69fdc0f","author":{"name":"Imre Deak","email":"30c82a474d1d4bae8c10f8236e904d91678ba81d@intel.com"},"message":"drm/i915/bxt: Set DDI PHY lane latency optimization during modeset\n\nSo far we configured a static lane latency optimization during driver\nloading/resuming. The specification changed at one point and now this\nconfiguration depends on the lane count, so move the configuration\nto modeset time accordingly.\n\nIt's not clear when this lane configuration takes effect. The\nspecification only requires that the programming is done before enabling\nthe port. On CHV OTOH the lanes start to power up already right after\nenabling the PLL. To be safe preserve the current order and set things\nup already before enabling the PLL.\n\nv2: (Ander)\n- Simplify the optimization mask calculation.\n- Use the correct pipe_config always during the calculation instead\n  of the bogus intel_crtc->config.\n\nCC: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>\nBugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95476\nSigned-off-by: Imre Deak <imre.deak@intel.com>\nReviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>\n\n[dsd: backport to 4.4]","distinct":false,"url":"https://api.github.com/repos/endlessm/linux/commits/c19792028cb5cd9ce34a0e506793ec98e69fdc0f"},{"sha":"288612e282c8383be159f9c3ffaf19b640236fc1","author":{"name":"Carlo Caione","email":"9ea996366aa1e904192e60d0d1415d0bef972448@caione.org"},"message":"Merge pull request #164 from endlessm/T13366-eos3\n\ndrm/i915/bxt: Set DDI PHY lane latency optimization during modeset","distinct":true,"url":"https://api.github.com/repos/endlessm/linux/commits/288612e282c8383be159f9c3ffaf19b640236fc1"}]}
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