{"push_id":988570609,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"274755757e93252334bff9929bbe9efe4d4d420c","before":"eb9757f6ecc539ee7ed55c37bc8e53e3df4eb4fa","commits":[{"sha":"274755757e93252334bff9929bbe9efe4d4d420c","author":{"email":"26294bcb01cdc361afe06a2787bab8d16e97ede5@apple.com","name":"Tim Northover"},"message":"ARM: sink atomic release barrier as far as possible into cmpxchg.\n\nDMB instructions can be expensive, so it's best to avoid them if possible. In\natomicrmw operations there will always be an attempted store so a release\nbarrier is always needed, but in the cmpxchg case we can delay the DMB until we\nknow we'll definitely try to perform a store (and so need release semantics).\n\nIn the strong cmpxchg case this isn't quite free: we must duplicate the LDREX\ninstructions to skip the barrier on subsequent iterations. The basic outline\nbecomes:\n\n        ldrex rOld, [rAddr]\n        cmp rOld, rDesired\n        bne Ldone\n        dmb\n    Lloop:\n        strex rRes, rNew, [rAddr]\n        cbz rRes Ldone\n        ldrex rOld, [rAddr]\n        cmp rOld, rDesired\n        beq Lloop\n    Ldone:\n\nSo we'll skip this version for strong operations in \"minsize\" functions.","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-submodule/commits/274755757e93252334bff9929bbe9efe4d4d420c"}]}