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high level layout\r\nof all PCBs including location of ICs, board-to-\r\nboard headers, RF shielding, heat sinks,\r\nmechanical support and front panel design","creator":{"login":"jordens","id":1338946,"avatar_url":"https://avatars.githubusercontent.com/u/1338946?v=3","gravatar_id":"","url":"https://api.github.com/users/jordens","html_url":"https://github.com/jordens","followers_url":"https://api.github.com/users/jordens/followers","following_url":"https://api.github.com/users/jordens/following{/other_user}","gists_url":"https://api.github.com/users/jordens/gists{/gist_id}","starred_url":"https://api.github.com/users/jordens/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jordens/subscriptions","organizations_url":"https://api.github.com/users/jordens/orgs","repos_url":"https://api.github.com/users/jordens/repos","events_url":"https://api.github.com/users/jordens/events{/privacy}","received_events_url":"https://api.github.com/users/jordens/received_events","type":"User","site_admin":false},"open_issues":6,"closed_issues":2,"state":"open","created_at":"2016-09-26T14:58:37Z","updated_at":"2016-10-09T10:06:05Z","due_on":null,"closed_at":null},"comments":1,"created_at":"2016-10-07T15:25:37Z","updated_at":"2016-10-09T10:06:05Z","closed_at":"2016-10-09T10:06:05Z","body":"Kintex Ultrascale -1 or -2 choice for price.\r\n\r\nThe only relevant difference that I can see right now is: (http://www.xilinx.com/support/documentation/data_sheets/ds892-kintex-ultrascale-data-sheet.pdf)\r\n\r\n* CPLL on -1 is 8.5 G max. That's not a problem for the 16 DAC TX GTH, but for the 4 SFP/SATA/AMC GTH TX they would need to be driven from the same QPLL if we want to run them faster than 8.5 G.\r\n\r\n@sbourdeauducq ok to choose -1 speed grade for price?"}}
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