{"action":"created","issue":{"url":"https://api.github.com/repos/softdevteam/warmup_experiment/issues/142","repository_url":"https://api.github.com/repos/softdevteam/warmup_experiment","labels_url":"https://api.github.com/repos/softdevteam/warmup_experiment/issues/142/labels{/name}","comments_url":"https://api.github.com/repos/softdevteam/warmup_experiment/issues/142/comments","events_url":"https://api.github.com/repos/softdevteam/warmup_experiment/issues/142/events","html_url":"https://github.com/softdevteam/warmup_experiment/pull/142","id":170620277,"number":142,"title":"TSR support","user":{"login":"vext01","id":604955,"avatar_url":"https://avatars.githubusercontent.com/u/604955?v=3","gravatar_id":"","url":"https://api.github.com/users/vext01","html_url":"https://github.com/vext01","followers_url":"https://api.github.com/users/vext01/followers","following_url":"https://api.github.com/users/vext01/following{/other_user}","gists_url":"https://api.github.com/users/vext01/gists{/gist_id}","starred_url":"https://api.github.com/users/vext01/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/vext01/subscriptions","organizations_url":"https://api.github.com/users/vext01/orgs","repos_url":"https://api.github.com/users/vext01/repos","events_url":"https://api.github.com/users/vext01/events{/privacy}","received_events_url":"https://api.github.com/users/vext01/received_events","type":"User","site_admin":false},"labels":[{"url":"https://api.github.com/repos/softdevteam/warmup_experiment/labels/enhancement","name":"enhancement","color":"84b6eb"},{"url":"https://api.github.com/repos/softdevteam/warmup_experiment/labels/help%20wanted","name":"help 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start looking at TSR support. Please don't merge yet, as discussion is required, and a few small tweaks.\r\n\r\nThere is going to be an accompanying krun change, which I will link shortly.\r\nEDIT: https://github.com/softdevteam/krun/pull/234\r\n\r\nIn short: We need to be able to get at the TSR register from all of the VMS.\r\n\r\nGetting at the TSR means ultimately calling inline assembler. There is a C function in libkrun to get at the TSR. If convinient (as is for Python and Lua) we simply call to libkrun. For other VMs where it is not so easy to call libraries, I've built the C function into the VM itself.\r\n\r\nNotes:\r\n * The TSR is a 64-bit unsigned value, but the numeric representaions of some languages can't represent this.\r\n  * Javascript and Lua only have doubles -- we *should* be OK (?)\r\n  * PHP has platform specific signed integers only. In HHVM I've attempted to work around this by only ever working on TSR values in C++ code. I'm not happy with it -- need to think more -- worst case, return a double.\r\n  * Java has no unsigned 64, but `long` (64-bit signed) can be interpreted as 64-bit unsiogned  if we are careful.\r\n * We should use the synchronising variant of the TSR instruction -- This will be the last change I make.\r\n\r\nI've reformatted the graphs, checked `--one-page` and `--interactive` work, but due to the massive TSR values, the Y-axis is kinda annoying:\r\n\r\n![tsr](https://cloud.githubusercontent.com/assets/604955/17586764/884f1308-5fbb-11e6-9fa8-59dc492c08d8.png)\r\n\r\nNote the weird axis offset/scale on the top right. (Also note the crossover of the wallclock and TSR time early on. This seems to be a recurring trend, interesting...). Not sure how we could present the graph better...\r\n\r\nWe all need to check this super-carefully.\r\n\r\nLater I'm going to run a small experiment and upload a result file for your inspection.\r\n\r\nLet the discussion begin."},"comment":{"url":"https://api.github.com/repos/softdevteam/warmup_experiment/issues/comments/239178706","html_url":"https://github.com/softdevteam/warmup_experiment/pull/142#issuecomment-239178706","issue_url":"https://api.github.com/repos/softdevteam/warmup_experiment/issues/142","id":239178706,"user":{"login":"vext01","id":604955,"avatar_url":"https://avatars.githubusercontent.com/u/604955?v=3","gravatar_id":"","url":"https://api.github.com/users/vext01","html_url":"https://github.com/vext01","followers_url":"https://api.github.com/users/vext01/followers","following_url":"https://api.github.com/users/vext01/following{/other_user}","gists_url":"https://api.github.com/users/vext01/gists{/gist_id}","starred_url":"https://api.github.com/users/vext01/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/vext01/subscriptions","organizations_url":"https://api.github.com/users/vext01/orgs","repos_url":"https://api.github.com/users/vext01/repos","events_url":"https://api.github.com/users/vext01/events{/privacy}","received_events_url":"https://api.github.com/users/vext01/received_events","type":"User","site_admin":false},"created_at":"2016-08-11T14:32:24Z","updated_at":"2016-08-11T14:32:24Z","body":"Looks like we are confused as to the meaning of the timestamp register:\r\n\r\n```\r\nThe processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever the processor is reset.\r\n```\r\n\r\nIt's nothing to do with the number of instructions executed. It's actually simply a measure of time.\r\n\r\nThe P variant waits for the pipeline to empty. I'm not sure we want that, since the pipeline includes future instructions. Am I right?\r\n\r\nIt's also good to know the TSR is zeroed on reboot."}}
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