{"push_id":1333759595,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"a837849b604fa41559ad154904ac712c9ede1b60","before":"b106f8d014d5825a46b3ffbc37190e9291ad7dc9","commits":[{"sha":"a837849b604fa41559ad154904ac712c9ede1b60","author":{"name":"Yichao Yu","email":"4c52a12f98ba76da5cabe1890eca4c883d4bf99a@gmail.com"},"message":"[designs/fpga_bo] WIP more parts","distinct":true,"url":"https://api.github.com/repos/nacs-lab/yyc-data/commits/a837849b604fa41559ad154904ac712c9ede1b60"}]}
{"actor":{"display_login":"yuyichao"}}