{"push_id":1208888244,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"530f0c21c62bf3ea4603b237a72b02e1b4541193","before":"5a04b09d43cb0186c95decd72dbae480b61a7d3c","commits":[{"sha":"4cead0b5646bc6167bce675268e5aac43febf0e2","author":{"name":"Matt Arsenault","email":"becd9ebb08babd166e3a53b1fe2c83834aceaa25@amd.com"},"message":"AMDGPU: Expand register indexing pseudos in custom inserter\n\nThis is to help moveSILowerControlFlow to before regalloc.\nThere are a couple of tradeoffs with this. The complete CFG\nis visible to more passes, the loop body avoids an extra copy of m0,\nvcc isn't required, and immediate offsets can be shrunk into s_movk_i32.\n\nThe disadvantage is the register allocator doesn't understand that\nthe single lane's vector is dead within the loop body, so an extra\nregister is used to outlive the loop block when expanding the\nVGPR -> m0 loop. This also now results in worse waitcnt insertion\nbefore the loop instead of after for pending operations at the point\nof the indexing, but that should be fixed by future improvements to\ncross block waitcnt insertion.\n\nv_movreld_b32's operands are now modeled more correctly since vdst\nis not a true output. This is kind of a hack to treat vdst as a\nuse operand. Extra checking is required in the verifier since\nI can't seem to get tablegen to emit an implicit operand for a\nvirtual register.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275934 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm/commits/4cead0b5646bc6167bce675268e5aac43febf0e2"},{"sha":"530f0c21c62bf3ea4603b237a72b02e1b4541193","author":{"name":"Matt Arsenault","email":"becd9ebb08babd166e3a53b1fe2c83834aceaa25@amd.com"},"message":"AMDGPU/SI: Fix SI scheduler refcount issue\n\nWithout this fix, releaseSuccessors when InOrOutBlock is\nfalse could release SUs outside the schedule BasicBlock.\n\nPatch by Axel Davy\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275935 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm/commits/530f0c21c62bf3ea4603b237a72b02e1b4541193"}]}
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