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Fix formatting.\n\nReviewed-by: Charmaine Lee <charmainel@vmware.com>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/b94f73c15066d434e44b60ddddb1d837b841c08f"},{"sha":"abc6432d54c4b4b50368f230634ed8a0d2c92e34","author":{"name":"Brian Paul","email":"496e153a9fb909fb693e8592e6df5f4bc45bdb28@vmware.com"},"message":"svga: fix copying non-zero layers of 1D array textures\n\nLike cube maps, we need to convert the z information to a layer index.\nAlso rename the *_face vars to *_face_layer to make things a little more\nunderstandable.\n\nReviewed-by: Charmaine Lee <charmainel@vmware.com>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/abc6432d54c4b4b50368f230634ed8a0d2c92e34"},{"sha":"05abaa65c745d74fb296006285b85d253cb11525","author":{"name":"Brian Paul","email":"496e153a9fb909fb693e8592e6df5f4bc45bdb28@vmware.com"},"message":"svga: try to flag surfaces for sampling, in addition to rendering\n\nThis silences some warnings when we try to sample from surfaces that were\ncreated for drawing, such as when blitting from one of the framebuffer\nsurfaces.  We were already doing the opposite situation (adding a bind\nflag for rendering to surfaces declared as texture sources).\n\nReviewed-by: Charmaine Lee <charmainel@vmware.com>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/05abaa65c745d74fb296006285b85d253cb11525"},{"sha":"68116dcd5a05508af06cd41ca14faab1b910a934","author":{"name":"Brian Paul","email":"496e153a9fb909fb693e8592e6df5f4bc45bdb28@vmware.com"},"message":"cso: null-out previously bound sampler states\n\nIf, for example, we previously had 2 sampler states bound and now we\nare binding one, we'd leave the second sampler state unchanged.\nThis change nulls-out the second sampler state in this situation.\nWe're already doing the same thing for sampler views.\n\nThis silences an occasional warning issued by the VMware driver when\nthe number of sampler views and sampler states disagreed.\n\nReviewed-by: Charmaine Lee <charmainel@vmware.com>\nReviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/68116dcd5a05508af06cd41ca14faab1b910a934"},{"sha":"ef5a31fc06d58ad655fd6b71ed3e939147e67108","author":{"name":"Brian Paul","email":"496e153a9fb909fb693e8592e6df5f4bc45bdb28@vmware.com"},"message":"gallium/util: change assertion to conditional in util_bitmask_destroy()\n\nIf we fail to create a context in the VMware driver we call this function\nunconditionally to free a bunch of bit vectors.  Instead of asserting on\na null pointer, just no-op.\n\nReviewed-by: Jose Fonseca <jfonseca@vmware.com>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/ef5a31fc06d58ad655fd6b71ed3e939147e67108"},{"sha":"75881bed9e12cee1abfb5ec466e17ff2b253e0ab","author":{"name":"Kenneth Graunke","email":"e8e0e12ced052a7b04539107b6dfbe9787d38bd2@whitecape.org"},"message":"i965: Rework the TCS passthrough shader to use NIR.\n\nI'm about to implement a scalar TCS backend, and I'd rather not\nduplicate all of this code there.\n\nOne change is that we now write the tessellation levels from all\nTCS threads, rather than just the first.  This is pretty harmless,\nand was easier.  The IF/ENDIF needed for that are gone; otherwise\nthe generated code is basically identical.\n\nI chose to emit load/store intrinsics directly because it was easier.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/75881bed9e12cee1abfb5ec466e17ff2b253e0ab"},{"sha":"7d9143ad885752184156b3a0d3e492aef09af3b0","author":{"name":"Kenneth Graunke","email":"e8e0e12ced052a7b04539107b6dfbe9787d38bd2@whitecape.org"},"message":"i965: Write a scalar TCS backend that runs in SINGLE_PATCH mode.\n\nUnlike most shader stages, the Hull Shader hardware makes us explicitly\ntell it how many threads to dispatch and manually configure the channel\nmask.  One perk of this is that we have a lot of flexibility - we can\nrun it in either SIMD4x2 or SIMD8 mode.\n\nTreating it as SIMD8 means that shaders with 8 or fewer output vertices\n(which is overwhemingly the common case) can be handled by a single\nthread.  This has several intriguing properties:\n\n- Accessing input arrays with gl_InvocationID as the index is a simple\n  SIMD8 URB read with g1 as the header.  No indirect addressing required.\n- Barriers are no-ops.\n- We could potentially do output shadowing to combine writes, as the\n  concurrency concerns are gone.  (We don't do this yet, though.)\n\nv2: Drop first_non_payload_grf change, as it was always adding 0\n    (caught by Jordan Justen).\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jordan Justen <jordan.l.justen@intel.com>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/7d9143ad885752184156b3a0d3e492aef09af3b0"},{"sha":"c55dc77ab13420a9fe0177ccd21a6b0a950d9113","author":{"name":"Francisco Jerez","email":"475862461d4f628eb34c6ff59c62fa061400c9c5@riseup.net"},"message":"i965: Pass devinfo pointer to brw_instruction_name().\n\nA future series will implement support for an instruction that happens\nto have the same opcode number as another instruction we support\nalready on a disjoint set of hardware generations.  In order to\ndisambiguate which instruction it is brw_instruction_name() will need\nsome way to find out which device we are generating code for.\n\nReviewed-by: Iago Toral Quiroga <itoral@igalia.com>\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/c55dc77ab13420a9fe0177ccd21a6b0a950d9113"},{"sha":"1cc7573162a7f0e8346d7abab50890c58a0dce9a","author":{"name":"Francisco Jerez","email":"475862461d4f628eb34c6ff59c62fa061400c9c5@riseup.net"},"message":"i965: Pass devinfo pointer to is_3src() helpers.\n\nThis is not strictly required for the following changes because none\nof the three-source opcodes we support at the moment in the compiler\nback-end has been removed or redefined, but that's likely to change in\nthe future.  In any case having hardware instructions specified as a\npair of hardware device and opcode number explicitly in all cases will\nsimplify the opcode look-up interface introduced in a subsequent\ncommit, since the opcode number alone is in general ambiguous.\n\nReviewed-by: Iago Toral Quiroga <itoral@igalia.com>\nReviewed-by: Matt Turner <mattst88@gmail.com>\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/1cc7573162a7f0e8346d7abab50890c58a0dce9a"},{"sha":"1530e27534831a8d1c82e0a82fe15cd9c70e61e6","author":{"name":"Francisco Jerez","email":"475862461d4f628eb34c6ff59c62fa061400c9c5@riseup.net"},"message":"i965/disasm: Wrap opcode_desc look-up in a function.\n\nThe function takes a device info struct as argument in addition to the\nopcode number in order to disambiguate between multiple opcode_desc\nentries for different instructions with the same opcode number.\n\nReviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v1]\n\n[v2] mattst88: Put brw_opcode_desc() in brw_eu.c instead of moving it\n               there in a later patch.\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v2]\n[v3] mattst88: Return NULL if opcode >= ARRAY_SIZE(opcode_descs)\nReviewed-by: Matt Turner <mattst88@gmail.com>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/1530e27534831a8d1c82e0a82fe15cd9c70e61e6"},{"sha":"d01596613b6b7831a3c6a596108a83340f8bf657","author":{"name":"Matt Turner","email":"54e31ea7f3468c01175d503617203fda9e1e02a1@gmail.com"},"message":"i965: Move inst_info from brw_eu_validate.c to brw_eu.c.\n\nDrop the uses of 'enum gen' to a plain int, so that we don't have to\nexpose the bitfield definitions and GEN_GE/GEN_LE macros to other users\nof brw_eu.h. As a result, s/.gen/.gens/ to avoid confusion with\ndevinfo->gen.\n\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/d01596613b6b7831a3c6a596108a83340f8bf657"},{"sha":"667408b889e2bf5f103340c2deeb04c4d99cb75b","author":{"name":"Matt Turner","email":"54e31ea7f3468c01175d503617203fda9e1e02a1@gmail.com"},"message":"i965: Merge inst_info and opcode_desc tables.\n\nI merged opcode_desc into inst_info (instead of the other way around)\nbecause inst_info was sorted by opcode number.\n\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/667408b889e2bf5f103340c2deeb04c4d99cb75b"},{"sha":"0ff4912cf4e3d7186bbc5ba4886d00dd4d4876d3","author":{"name":"Matt Turner","email":"54e31ea7f3468c01175d503617203fda9e1e02a1@gmail.com"},"message":"i965: Actually check whether the opcode is supported.\n\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/0ff4912cf4e3d7186bbc5ba4886d00dd4d4876d3"},{"sha":"b89b0a03f292d812e4b06b0260b00a56532db689","author":{"name":"Matt Turner","email":"54e31ea7f3468c01175d503617203fda9e1e02a1@gmail.com"},"message":"i965: Make opcode_descs and gen_from_devinfo() static.\n\nThe previous commit replaced direct uses of opcode_descs with calls to\nthe wrapper function, which should be the only method of accessing\nopcode_descs's data. As a result gen_from_devinfo() can also be made\nstatic.\n\nReviewed-by: Kenneth Graunke <kenneth@whitecape.org>","distinct":false,"url":"https://api.github.com/repos/victoredwardocallaghan/mesa-GLwork/commits/b89b0a03f292d812e4b06b0260b00a56532db689"}]}
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