{"push_id":1107600885,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"57215d5b85193c6b0a4dfdc6ac86f586b1e80a94","before":"b68f1bd5aaf62653b90e752327187cb704bde94c","commits":[{"sha":"058f70b61a00b7f0c4d2fc2505399aaeb1bb0e90","author":{"email":"866e0609322e56f5df31cacb2e900e3c3d15d360@138bc75d-0d04-0410-961f-82ee72b054a4","name":"amonakov"},"message":"genautomata.c cleanup\n\n\t* genattr.c (main): Change 'rtx' to 'rtx_insn *' in prototypes of\n\t'insn_latency', 'maximal_insn_latency', 'min_insn_conflict_delay'.\n\t* genautomata.c (output_internal_insn_code_evaluation): Simplify.\n\tMove handling of non-insn arguments inline into the sole user:\n\t(output_trans_func): ...here.\n\t(output_min_insn_conflict_delay_func): Change 'rtx' to 'rtx_insn *'\n\tin emitted function prototype.\n\t(output_internal_insn_latency_func): Ditto.  Simplify.\n\t(output_internal_maximal_insn_latency_func): Ditto.  Delete\n\talways-unused argument.\n\t(output_insn_latency_func): Ditto.\n\t(output_maximal_insn_latency_func): Ditto.\n \n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236132 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/058f70b61a00b7f0c4d2fc2505399aaeb1bb0e90"},{"sha":"67d3121cc7a2193c151a925e8c6cfe407c2df7cf","author":{"email":"4e862574c3bcf592f98137122f06a10f88451403@138bc75d-0d04-0410-961f-82ee72b054a4","name":"meissner"},"message":"[gcc]\n2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>\n\n\t* config/rs6000/predicates.md (quad_memory_operand): Move most of\n\tthe code into quad_address_p and call it to share code with\n\tvsx_quad_dform_memory_operand.\n\t(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector\n\td-form support.\n\t* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask\n\tbit instead of being a separate word.  Split -mpower9-dform into\n\ttwo switches, -mpower9-dform-scalar and -mpower9-dform-vector.\n\t* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask\n\tfor the register class supporting 128-bit quad word memory\n\toffsets.\n\t(mode_supports_vsx_dform_quad): Helper function to return if the\n\tregister class uses quad word memory offsets.\n\t(rs6000_debug_addr_mask): Add support for quad word memory\n\toffsets.\n\t(rs6000_debug_reg_global): Always print if we are using LRA or\n\tnot.\n\t(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form\n\tinstructions are enabled, set up the appropriate addr_masks for\n\t128-bit types.\n\t(rs6000_init_hard_regno_mode_ok): wb constraint is now based on\n\t-mpower9-dform-scalar, instead of -mpower9-dform.\n\t(rs6000_option_override_internal): Split -mpower9-dform into two\n\tswitches, -mpower9-dform-scalar and -mpower9-dform-vector.  The\n\t-mpower9-dform switch sets or clears both.  If we are not using\n\tthe LRA register allocator, do not enable -mpower9-dform-vector by\n\tdefault.  If we are using LRA, enable -mpower9-dform-vector and\n\t-mvsx-timode if it is appropriate.  Issue a warning if either\n\t-mpower9-dform-vector or -mvsx-timode are explicitly used without\n\tenabling LRA.\n\t(quad_address_offset_p): New helper function to return if the\n\toffset is legal for quad word memory instructions.\n\t(quad_address_p): New function to determin if GPR or vector\n\tregister quad word memory addresses are legal.\n\t(mem_operand_gpr): Validate quad word address offsets.\n\t(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector\n\td-form (register + offset) instructions.\n\t(offsettable_ok_by_alignment): Likewise.\n\t(rs6000_legitimate_offset_address_p): Likewise.\n\t(legitimate_lo_sum_address_p): Likewise.\n\t(rs6000_legitimize_address): Likewise.\n\t(rs6000_legitimize_reload_address): Add more debug statements for\n\t-mdebug=addr.\n\t(rs6000_legitimate_address_p): Add support for ISA 3.0 vector\n\td-form instructions.\n\t(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector\n\td-form instructions.  Distinguish different cases in debug\n\toutput.\t(rs6000_secondary_reload_inner): Add support for ISA 3.0 vector\n\td-form instructions.\n\t(rs6000_preferred_reload_class): Likewise.\n\t(rs6000_output_move_128bit): Add support for ISA 3.0 d-form\n\tinstructions.  If ISA 3.0 is available, generate lxvx/stxvx instead\n\tof the ISA 2.06 indexed memory instructions.\n\t(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,\n\tuse them to save/restore the saved vector registers instead of\n\tusing Altivec instructions.\n\t(rs6000_emit_epilogue): Likewise.\n\t(rs6000_lra_p): Use TARGET_LRA instead of the old option word.\n\t(rs6000_opt_masks): Split -mpower9-dform into\n\t-mpower9-dform-scalar and -mpower9-dform-vector.\n\t(rs6000_print_options_internal): Print -mno-<switch> if <switch>\n\twas not selected.\n\t* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit\n\tISA 3.0 vector indexed memory instructions, and fold the code into\n\tthe normal mov<mode> patterns.\n\t(p9_vecstore_<mode>): Likewise.\n\t(vsx_mov<mode>): Add support for ISA 3.0 vector d-form\n\tinstructions.\n\t(vsx_movti_64bit): Likewise.\n\t(vsx_movti_32bit): Likewise.\n\t* config/rs6000/constraints.md (wO constraint): New constraint for\n\tISA 3.0 vector d-form support.\n\t* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use\n\t-mpower9-dform-scalar instead of -mpower9-dform.  Add note not to\n\tinclude -mpower9-dform-vector until we switch over to LRA.\n\t(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two. \n\tswitches, -mpower9-dform-scalar and -mpower9-dform-vector.\n\t* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.\n\t* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation\n\tfor -mpower9-dform and -mlra.\n\t* doc/md.texi (wO constraint): Document wO constraint.\n\n[gcc/testsuite]\n2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>\n\n\t* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form\n\tsupport.\n\t* gcc.target/powerpc/dform-1.c: Add -mlra option to silence\n\twarning when using -mvsx-timode.\n\t* gcc.target/powerpc/p8vector-int128-1.c: Likewise.\n\t* gcc.target/powerpc/dform-2.c: Likewise.\n\t* gcc.target/powerpc/pr68805.c: Likewise.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236133 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/67d3121cc7a2193c151a925e8c6cfe407c2df7cf"},{"sha":"93554178cc752bc67c5c8b018f71a98d5710425f","author":{"email":"2401bc1003df5c832d17391d0035b6b98ec15e37@138bc75d-0d04-0410-961f-82ee72b054a4","name":"uros"},"message":"\t* config/i386/i386.c (legitimize_pic_address): Use\n\tcopy_to_suggested_reg instead of gen_movsi.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236138 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/93554178cc752bc67c5c8b018f71a98d5710425f"},{"sha":"57215d5b85193c6b0a4dfdc6ac86f586b1e80a94","author":{"email":"2401bc1003df5c832d17391d0035b6b98ec15e37@138bc75d-0d04-0410-961f-82ee72b054a4","name":"uros"},"message":"\t* gcc.target/i386/sse-13.c: Add dg-add-options bind_pic_locally\n\tdirective.\n\t* gcc.target/i386/pr66746.c: Ditto.\n\n\n\ngit-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@236140 138bc75d-0d04-0410-961f-82ee72b054a4","distinct":true,"url":"https://api.github.com/repos/kraj/gcc/commits/57215d5b85193c6b0a4dfdc6ac86f586b1e80a94"}]}