{"push_id":1314912755,"size":54,"distinct_size":2,"ref":"refs/heads/unph-master","head":"89b31de708846a767c76a015764f58b0a27d81a5","before":"d05217c75b9dd7df8c3a17ea23c6171e45a02f30","commits":[{"sha":"63ebf051b09a4f328de9a124cd18c8634ad2600a","author":{"name":"Tony Xie","email":"5ee08146a197f82ce96d4ef0b1ac83dc272907d8@rock-chips.com"},"message":"rockchip: fix the scu idle for rk3399\n\nAs rk3399 reported the d8/octane scores drop 10% with cpu idle.\nThe root cause is thc cpu cluster enter the slow mode.\nWe don't need switch the clock to 24MHz if cpu cluster enter the\nretention mode. In order to improve performance, it just needs for\ncluster enter powering off mode.\n\nAlso, we shouldn't do anything for hlvl if the system is off.\n\nChange-Id: I2a02962a01343abd0cba47ed63192c1cdf88b119","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/63ebf051b09a4f328de9a124cd18c8634ad2600a"},{"sha":"77b05323921c23e4261ddd8fee5c326a79b0af97","author":{"name":"davidcunado-arm","email":"5bc5ae1325b1b29e8da0fc707478fe905c353138@arm.com"},"message":"Merge pull request #697 from rockchip-linux/fixes-scu-idle\n\nrockchip: fix the scu idle for rk3399","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/77b05323921c23e4261ddd8fee5c326a79b0af97"},{"sha":"7a3d4bdeefe361d8b88d0a62251df768a73684b3","author":{"name":"Soby Mathew","email":"28ac8a8a37533dcf0678f8f7a843a3846f8bd4be@arm.com"},"message":"Flush `psci_plat_pm_ops` after initialization\n\nThe `psci_plat_pm_ops` global pointer is initialized during cold boot by the\nprimary CPU and will be accessed by the secondary CPUs before enabling data\ncache during warm boot. This patch adds a missing data cache flush of\n`psci_plat_psci_ops` after initialization during psci_setup() so that\nsecondaries can see the updated `psci_plat_psci_ops` pointer.\n\nFixes ARM-software/tf-issues#424\n\nChange-Id: Id4554800b5646302b944115a33be69507d53cedb","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/7a3d4bdeefe361d8b88d0a62251df768a73684b3"},{"sha":"536c2492456758d2fe7e28b11ece9001c4d79cc0","author":{"name":"Caesar Wang","email":"ad26c0afdf9bdf5f54c09db097f9e17e73167ec1@rock-chips.com"},"message":"rockchip/rk3399: improve gpio driver and support get pull mode function\n\nWe may need gpio pull mode later, so add this function.\nBesides fix a set pull mode bug, and save gpio clock gate,\nwhen operate the gpio, we will enable gpio clock, when\nfinish gpio operate, restore gpio clock gate status.\n\nChange-Id: Ia1d602804f571a17f5ddc499908663b968b02974","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/536c2492456758d2fe7e28b11ece9001c4d79cc0"},{"sha":"e550c6310118d1369796751ce98fe66167db0861","author":{"name":"Caesar Wang","email":"ad26c0afdf9bdf5f54c09db097f9e17e73167ec1@rock-chips.com"},"message":"rockchip: support disable/enable specific gpio when suspend/resume\n\nsome specific board need to disable/enable specific gpio when\nsuspend/resume, so we add this function, bootloader can pass the\nspecific gpio, and we can handle these gpios in bl31 suspend/resuem\nfunction.\n\nChange-Id: I373b03ef9202ee4a05a2b9caacdfa01b47ee2177","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/e550c6310118d1369796751ce98fe66167db0861"},{"sha":"2bff35bb7c3a20edddce8c5c3bfa8d7e948679e9","author":{"name":"Caesar Wang","email":"ad26c0afdf9bdf5f54c09db097f9e17e73167ec1@rock-chips.com"},"message":"rockchip: set gpio2 ~ gpio4 to input and pull none mode\n\nFor save power cosumption, if gpio power supply shut down, we need to\nset gpio2 ~ gpio4 to input and HiZ status when suspend, and recovery\nthey status when rusume. we do it base on apio pass from loader.\n\nChange-Id: I59fd2395e5e37e63425472a39f519822c9197e4c","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/2bff35bb7c3a20edddce8c5c3bfa8d7e948679e9"},{"sha":"a8656400c464ac5ae83cf8949caefe915ba2bb14","author":{"name":"Caesar Wang","email":"ad26c0afdf9bdf5f54c09db097f9e17e73167ec1@rock-chips.com"},"message":"rockchip: SIP call use 32 bit return value for rk3399\n\nfor compatible 32bit and 64bit, we use 0x82xxxxxx as function ID,\nwe modify SIP call function return value to 32 bit.\n\nChange-Id: Ib99b03a9ea423853aaa296dcc634ee82c622a552","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/a8656400c464ac5ae83cf8949caefe915ba2bb14"},{"sha":"7e1bedb697613dbdbeba39abdaf43dc751b5a578","author":{"name":"Caesar Wang","email":"ad26c0afdf9bdf5f54c09db097f9e17e73167ec1@rock-chips.com"},"message":"rockchip: fixes some typo\n\nAs the checkpatch reports the warning or error.\n\nplat/rockchip/common/plat_pm.c:96:\nERROR: do not set execute permissions for source files\nplat/rockchip/rk3399/drivers/pmu/pmu.c:294:\nERROR: do not set execute permissions for source files\n\nplat/rockchip/common/plat_pm.c:286: WARNING: line over 80 characters\nplat/rockchip/common/plat_pm.c:287: WARNING: line over 80 characters\n\nChange-Id: Ib347da21c56551c31df3f90f03777b13c75d5c26","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/7e1bedb697613dbdbeba39abdaf43dc751b5a578"},{"sha":"048d802a087b2c52bd5e817cb8e0bc52ea6260ad","author":{"name":"danh-arm","email":"68a34f7dc4bfd6205eee9b3d985a5ef6c2a94040@arm.com"},"message":"Merge pull request #699 from soby-mathew/sm/flush_plat_psci_ops\n\nFlush `psci_plat_pm_ops` after initialization","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/048d802a087b2c52bd5e817cb8e0bc52ea6260ad"},{"sha":"c1ff80b1289df2c6d950413eab37cdd999b462a6","author":{"name":"Leon Chen","email":"955535cb88e892f5de76686c937cb769fd47bf8e@mediatek.com"},"message":"Support for Mediatek MT6795 SoC\n\nThis patch support single core to boot to Linux kernel\nthrough Trusted Firmware.\nIt also support 32 bit kernel and 64 bit kernel booting.","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/c1ff80b1289df2c6d950413eab37cdd999b462a6"},{"sha":"9df69ba37f3dd3a3f02fc8c0ba41236960b6b771","author":{"name":"dp-arm","email":"85a33b5dd3c6fb868048d5df72df51a994b4344b@arm.com"},"message":"fiptool: Add support for printing the sha256 digest with info command\n\nThis feature allows one to quickly verify that the expected\nimage is contained in the FIP without extracting the image and\nrunning sha256sum(1) on it.\n\nThe sha256 digest is only shown when the verbose flag is used.\n\nThis change requires libssl-dev to be installed in order to build\nTrusted Firmware. Previously, libssl-dev was optionally needed only\nto support Trusted Board Boot configurations.\n\nFixes ARM-Software/tf-issues#124\n\nChange-Id: Ifb1408d17f483d482bb270a589ee74add25ec5a6","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/9df69ba37f3dd3a3f02fc8c0ba41236960b6b771"},{"sha":"6083c841d0c43f2136921156abef7b684dce7bf0","author":{"name":"Yatharth Kochar","email":"717ab04ca336be64277e711ee1096558312a35cc@arm.com"},"message":"GICv3: Allow either G1S or G0 interrupts to be configured\n\nCurrently the GICv3 driver mandates that platform populate\nboth G1S and G0 interrupts. However, it is possible that a\ngiven platform is not interested in both the groups and\njust needs to specify either one of them.\n\nThis patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()`\nfunctions to allow either G1S or G0 interrupts to be configured.\n\nFixes ARM-software/tf-issues#400\n\nChange-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/6083c841d0c43f2136921156abef7b684dce7bf0"},{"sha":"4531d3c9ab409fc5df2d865620587a12f9fe7f3c","author":{"name":"davidcunado-arm","email":"5bc5ae1325b1b29e8da0fc707478fe905c353138@arm.com"},"message":"Merge pull request #698 from rockchip-linux/set-APIO-for-rk3399\n\nSet apio for rk3399","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/4531d3c9ab409fc5df2d865620587a12f9fe7f3c"},{"sha":"0587788abcd4daf98a8bef1f9545a9841e1015a8","author":{"name":"Caesar Wang","email":"ad26c0afdf9bdf5f54c09db097f9e17e73167ec1@rock-chips.com"},"message":"rockchip: fixes the gic panic for rk3399 resume\n\nWe make sure the resuming of gic need to be enabled.\nOtherwise, The resume will hit the below panic.\n...\n[   24.230541] CPU0: update max cpu_capacity 451\n[   24.236029] CPU5: update max cpu_capacity 1024\n[   24.236046] CPU4: shutdown\n[   24.243205] psci: CPU4 killed.\n[   24.258730] CPU5: shutdown\n[   24.261472] psci: CPU5 killed.\n[   24.270417] GIC: unable to set SRE (disabled at EL2), panic ahead\n[   24.270417] cat[7801]: undefined instruction: pc=ffffffc0004e65d0\n[   24.270417] Code: b0003940 91274400 97f871af d2801e00 (d5184600)\n[   24.270417] Internal error: Oops - undefined instruction: 0 [#1] PREEMPT\n\nChange-Id: Ie9542c8d5768ba0accfa073453da8bfe06d4f921","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/0587788abcd4daf98a8bef1f9545a9841e1015a8"},{"sha":"b1887a86aae9d52d5333251d6056478c470b59f0","author":{"name":"davidcunado-arm","email":"5bc5ae1325b1b29e8da0fc707478fe905c353138@arm.com"},"message":"Merge pull request #703 from rockchip-linux/fixes-gic-panic\n\nrockchip: fixes the gic panic for rk3399 resume","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/b1887a86aae9d52d5333251d6056478c470b59f0"},{"sha":"e1cb4da465d13bb7bc641985863421d8ec36d8f7","author":{"name":"Soren Brinkmann","email":"33f40dd66893b55edbfa29cb1b4b76fc26c24299@xilinx.com"},"message":"zynqmp: Add support for generic_delay_timer\n\nInitialize the generic_delay_timer in the zynqmp port.\n\nSigned-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/e1cb4da465d13bb7bc641985863421d8ec36d8f7"},{"sha":"2c239f7c2ab9979b2c3f151ed010ba3fb324f910","author":{"name":"Mirela Simonovic","email":"6d2b9d738ae8ec9fb269724cfebf0e1ddfe07358@aggios.com"},"message":"zynqmp: pm: Added NODE_IPI_RPU_0 node definition in pm_defs\n\nNodes represent IPI dedicated to the RPU (not accessible by APU)\n\nSigned-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/2c239f7c2ab9979b2c3f151ed010ba3fb324f910"},{"sha":"538957d85bf6d804139f329a8838275e95988a5e","author":{"name":"Soren Brinkmann","email":"33f40dd66893b55edbfa29cb1b4b76fc26c24299@xilinx.com"},"message":"zynqmp: Set RESET_TO_BL31 through platform.mk\n\nZynqMP only supports builds with RESET_TO_BL31=1. Set this option\nthrough the platform makefile on default.\n\nSigned-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/538957d85bf6d804139f329a8838275e95988a5e"},{"sha":"06526c9797c4f036e612602fb5a2ca20d80ad1bf","author":{"name":"Naga Sureshkumar Relli","email":"59cf4a7330d9b10e67737b652ea29e1509ba4c77@xilinx.com"},"message":"zynqmp: Add RW access to L2ACTLR_EL1 and CPUACTLR_EL1\n\nArm provided error injection support. To enable this error injection,\nwe need to set L2DEIEN in L2ACTLR_EL1 register and L1DEIEN in\nCPUACTLR_EL1 register.\n\nThis is needed for our cortexa53 edac linux driver testing.\nThese registers need write access from non secure EL1 i.e linux\nat the time of setting the above bits.\n\nSigned-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/06526c9797c4f036e612602fb5a2ca20d80ad1bf"},{"sha":"0ab6a2429b88015c809b3feff8eb645a1babdf6e","author":{"name":"Soren Brinkmann","email":"33f40dd66893b55edbfa29cb1b4b76fc26c24299@xilinx.com"},"message":"zynqmp: Change default BL31 address space\n\nThe OCM space was reorganized to use the space more efficiently. Adjust\nthe default ATF location to be aligned with other ZynqMP software\ncomponents.\n\nSigned-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>","distinct":false,"url":"https://api.github.com/repos/masahir0y/arm-trusted-firmware-yamada/commits/0ab6a2429b88015c809b3feff8eb645a1babdf6e"}]}
{"actor":{"display_login":"masahir0y"}}