{"action":"published","release":{"url":"https://api.github.com/repos/SebastianBoe/turborav/releases/2834080","assets_url":"https://api.github.com/repos/SebastianBoe/turborav/releases/2834080/assets","upload_url":"https://uploads.github.com/repos/SebastianBoe/turborav/releases/2834080/assets{?name,label}","html_url":"https://github.com/SebastianBoe/turborav/releases/tag/v0.2.0","id":2834080,"tag_name":"v0.2.0","target_commitish":"master","name":"Xilinx ISE-free release!","draft":false,"author":{"login":"SebastianBoe","id":609230,"avatar_url":"https://avatars.githubusercontent.com/u/609230?v=3","gravatar_id":"","url":"https://api.github.com/users/SebastianBoe","html_url":"https://github.com/SebastianBoe","followers_url":"https://api.github.com/users/SebastianBoe/followers","following_url":"https://api.github.com/users/SebastianBoe/following{/other_user}","gists_url":"https://api.github.com/users/SebastianBoe/gists{/gist_id}","starred_url":"https://api.github.com/users/SebastianBoe/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/SebastianBoe/subscriptions","organizations_url":"https://api.github.com/users/SebastianBoe/orgs","repos_url":"https://api.github.com/users/SebastianBoe/repos","events_url":"https://api.github.com/users/SebastianBoe/events{/privacy}","received_events_url":"https://api.github.com/users/SebastianBoe/received_events","type":"User","site_admin":false},"prerelease":false,"created_at":"2016-03-16T17:50:50Z","published_at":"2016-03-17T17:45:53Z","assets":[{"url":"https://api.github.com/repos/SebastianBoe/turborav/releases/assets/1440898","id":1440898,"name":"turborav.0.2.0.tar.gz","label":null,"uploader":{"login":"SebastianBoe","id":609230,"avatar_url":"https://avatars.githubusercontent.com/u/609230?v=3","gravatar_id":"","url":"https://api.github.com/users/SebastianBoe","html_url":"https://github.com/SebastianBoe","followers_url":"https://api.github.com/users/SebastianBoe/followers","following_url":"https://api.github.com/users/SebastianBoe/following{/other_user}","gists_url":"https://api.github.com/users/SebastianBoe/gists{/gist_id}","starred_url":"https://api.github.com/users/SebastianBoe/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/SebastianBoe/subscriptions","organizations_url":"https://api.github.com/users/SebastianBoe/orgs","repos_url":"https://api.github.com/users/SebastianBoe/repos","events_url":"https://api.github.com/users/SebastianBoe/events{/privacy}","received_events_url":"https://api.github.com/users/SebastianBoe/received_events","type":"User","site_admin":false},"content_type":"application/gzip","state":"uploaded","size":41419277,"download_count":0,"created_at":"2016-03-17T17:35:13Z","updated_at":"2016-03-17T17:36:17Z","browser_download_url":"https://github.com/SebastianBoe/turborav/releases/download/v0.2.0/turborav.0.2.0.tar.gz"}],"tarball_url":"https://api.github.com/repos/SebastianBoe/turborav/tarball/v0.2.0","zipball_url":"https://api.github.com/repos/SebastianBoe/turborav/zipball/v0.2.0","body":"### Release notes\r\nThis is the first release with support for the free and open\r\nsource synthesis flow IceStorm. With this the project\r\nis now free of all closed source software.\r\n\r\nXilinx ISE was supported in the previous release, but because it\r\nis awkward to use and package this support will from here on\r\nout be subject to bit rot and will not be tested in continuous\r\nintegration.\r\n\r\nThe Xilinx ISE + Spartan-3E FPGA synthesis flow produced a design\r\nwith 2 779 LUTs and a clock frequency of 50 MHz. The new open\r\nsource flow that uses an iCE40 FPGA is producing a design that\r\ncan be clocked at 22-25 MHz and uses 3988 Logic Cells. Because\r\nthe FPGAs are different it is difficult to compare the two\r\nreleases.\r\n\r\n[hw/src/test/c](hw/src/test/c)\r\nThis release adds support for having tests in the form of C-code\r\nfirmwares that run on the SoC. This type of testing is useful for\r\nsystem testing and developing tests that are portable to\r\nRTL/FPGA/ASIC.\r\n\r\n\r\n[hw/src/synth/yosys/icoboard](hw/src/synth/yosys/icoboard)\r\nSupport has been added for icoBOARD. An open HW project that\r\nsupports the IceStorm flow with a RaspberryPi 2 hat. To synthesize\r\nFPGA netlists for this board invoke scons with the build/synth/yosys/icoboard\r\ntarget.\r\n\r\n### Full release build log\r\n\r\n$ time scons build/test build/synth/yosys\r\nscons: Reading SConscript files ...\r\nscons: done reading SConscript files.\r\nscons: Building targets ...\r\nfsc -feature -deprecation -language:reflectiveCalls -Xlint -Xlint:-nullary-unit -Xfatal-warnings -classpath /usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar -d build/scala/classes build/main/scala/*.scala build/test/scala/*.scala build/test/scala/tb/*.scala && jar cf build/scala/classes/TurboRav.jar -C build/scala/classes TurboRav\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/add.o build/test/riscv/rv32ui/add.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -o build/misc/crt0.o build/misc/crt0.s\r\ngcc -E -P build/linker_script/turborav.ld.S > build/linker_script/turborav.ld\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/addi.o build/test/riscv/rv32ui/addi.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/and.o build/test/riscv/rv32ui/and.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/andi.o build/test/riscv/rv32ui/andi.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/auipc.o build/test/riscv/rv32ui/auipc.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/beq.o build/test/riscv/rv32ui/beq.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/bge.o build/test/riscv/rv32ui/bge.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/bgeu.o build/test/riscv/rv32ui/bgeu.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/blt.o build/test/riscv/rv32ui/blt.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/bltu.o build/test/riscv/rv32ui/bltu.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/bne.o build/test/riscv/rv32ui/bne.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/div.o build/test/riscv/rv32ui/div.S\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/bge -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/bge.map build/test/riscv/rv32ui/bge.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/andi -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/andi.map build/test/riscv/rv32ui/andi.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/beq -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/beq.map build/test/riscv/rv32ui/beq.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/bgeu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/bgeu.map build/test/riscv/rv32ui/bgeu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/blt -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/blt.map build/test/riscv/rv32ui/blt.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/bltu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/bltu.map build/test/riscv/rv32ui/bltu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/bne -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/bne.map build/test/riscv/rv32ui/bne.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/addi -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/addi.map build/test/riscv/rv32ui/addi.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/and -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/and.map build/test/riscv/rv32ui/and.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/add -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/add.map build/test/riscv/rv32ui/add.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/div -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/div.map build/test/riscv/rv32ui/div.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/auipc -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/auipc.map build/test/riscv/rv32ui/auipc.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/divu.o build/test/riscv/rv32ui/divu.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/j.o build/test/riscv/rv32ui/j.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/jal.o build/test/riscv/rv32ui/jal.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/jalr.o build/test/riscv/rv32ui/jalr.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/lb.o build/test/riscv/rv32ui/lb.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/lbu.o build/test/riscv/rv32ui/lbu.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/lh.o build/test/riscv/rv32ui/lh.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/lhu.o build/test/riscv/rv32ui/lhu.S\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/j -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/j.map build/test/riscv/rv32ui/j.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/divu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/divu.map build/test/riscv/rv32ui/divu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/jal -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/jal.map build/test/riscv/rv32ui/jal.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/jalr -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/jalr.map build/test/riscv/rv32ui/jalr.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/lb -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/lb.map build/test/riscv/rv32ui/lb.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/lbu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/lbu.map build/test/riscv/rv32ui/lbu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/lh -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/lh.map build/test/riscv/rv32ui/lh.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/lhu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/lhu.map build/test/riscv/rv32ui/lhu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/lui.o build/test/riscv/rv32ui/lui.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/lw.o build/test/riscv/rv32ui/lw.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/mul.o build/test/riscv/rv32ui/mul.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/mulh.o build/test/riscv/rv32ui/mulh.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/mulhsu.o build/test/riscv/rv32ui/mulhsu.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/mulhu.o build/test/riscv/rv32ui/mulhu.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/or.o build/test/riscv/rv32ui/or.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/ori.o build/test/riscv/rv32ui/ori.S\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/mul -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/mul.map build/test/riscv/rv32ui/mul.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/lw -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/lw.map build/test/riscv/rv32ui/lw.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/lui -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/lui.map build/test/riscv/rv32ui/lui.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/mulhu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/mulhu.map build/test/riscv/rv32ui/mulhu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/mulh -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/mulh.map build/test/riscv/rv32ui/mulh.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/mulhsu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/mulhsu.map build/test/riscv/rv32ui/mulhsu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/or -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/or.map build/test/riscv/rv32ui/or.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/ori -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/ori.map build/test/riscv/rv32ui/ori.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/rem.o build/test/riscv/rv32ui/rem.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/remu.o build/test/riscv/rv32ui/remu.S\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/add > build/test/riscv/rv32ui/add.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/addi > build/test/riscv/rv32ui/addi.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/and > build/test/riscv/rv32ui/and.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/andi > build/test/riscv/rv32ui/andi.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/auipc > build/test/riscv/rv32ui/auipc.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/beq > build/test/riscv/rv32ui/beq.dis\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/rem -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/rem.map build/test/riscv/rv32ui/rem.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/remu -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/remu.map build/test/riscv/rv32ui/remu.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/bge > build/test/riscv/rv32ui/bge.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/bgeu > build/test/riscv/rv32ui/bgeu.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/blt > build/test/riscv/rv32ui/blt.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/bltu > build/test/riscv/rv32ui/bltu.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/bne > build/test/riscv/rv32ui/bne.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/div > build/test/riscv/rv32ui/div.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/divu > build/test/riscv/rv32ui/divu.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/j > build/test/riscv/rv32ui/j.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/jal > build/test/riscv/rv32ui/jal.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/jalr > build/test/riscv/rv32ui/jalr.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/lb > build/test/riscv/rv32ui/lb.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/lbu > build/test/riscv/rv32ui/lbu.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/lh > build/test/riscv/rv32ui/lh.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/lhu > build/test/riscv/rv32ui/lhu.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/lui > build/test/riscv/rv32ui/lui.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/lw > build/test/riscv/rv32ui/lw.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/mul > build/test/riscv/rv32ui/mul.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/mulh > build/test/riscv/rv32ui/mulh.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/mulhsu > build/test/riscv/rv32ui/mulhsu.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/mulhu > build/test/riscv/rv32ui/mulhu.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/or > build/test/riscv/rv32ui/or.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/ori > build/test/riscv/rv32ui/ori.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/rem > build/test/riscv/rv32ui/rem.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/remu > build/test/riscv/rv32ui/remu.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/sb.o build/test/riscv/rv32ui/sb.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/sh.o build/test/riscv/rv32ui/sh.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/simple.o build/test/riscv/rv32ui/simple.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/sll.o build/test/riscv/rv32ui/sll.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/slli.o build/test/riscv/rv32ui/slli.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/slt.o build/test/riscv/rv32ui/slt.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/slti.o build/test/riscv/rv32ui/slti.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/sra.o build/test/riscv/rv32ui/sra.S\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/sb -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/sb.map build/test/riscv/rv32ui/sb.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/sh -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/sh.map build/test/riscv/rv32ui/sh.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/simple -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/simple.map build/test/riscv/rv32ui/simple.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/sll -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/sll.map build/test/riscv/rv32ui/sll.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/slli -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/slli.map build/test/riscv/rv32ui/slli.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/slt -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/slt.map build/test/riscv/rv32ui/slt.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/slti -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/slti.map build/test/riscv/rv32ui/slti.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/sh > build/test/riscv/rv32ui/sh.dis\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/sra -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/sra.map build/test/riscv/rv32ui/sra.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/sb > build/test/riscv/rv32ui/sb.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/simple > build/test/riscv/rv32ui/simple.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/sll > build/test/riscv/rv32ui/sll.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/slt > build/test/riscv/rv32ui/slt.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/slli > build/test/riscv/rv32ui/slli.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/slti > build/test/riscv/rv32ui/slti.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/sra > build/test/riscv/rv32ui/sra.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/srai.o build/test/riscv/rv32ui/srai.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/srl.o build/test/riscv/rv32ui/srl.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/srli.o build/test/riscv/rv32ui/srli.S\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/sub.o build/test/riscv/rv32ui/sub.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/sw.o build/test/riscv/rv32ui/sw.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/xor.o build/test/riscv/rv32ui/xor.S\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-gcc -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv -c -o build/test/riscv/rv32ui/xori.o build/test/riscv/rv32ui/xori.S\r\nriscv64-unknown-elf-gcc -o build/programs/input2output.o -c -O3 -Os -static -c -m32 -Wa,-march=RVIMAFDXhwacha --std=gnu11 -Ibuild/test/riscv/p -Ibuild/test/riscv build/programs/input2output.c\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/srai -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/srai.map build/test/riscv/rv32ui/srai.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/srl -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/srl.map build/test/riscv/rv32ui/srl.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/srli -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/srli.map build/test/riscv/rv32ui/srli.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/sub -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/sub.map build/test/riscv/rv32ui/sub.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/xor -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/xor.map build/test/riscv/rv32ui/xor.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/sw -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/sw.map build/test/riscv/rv32ui/sw.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-ld -o build/test/riscv/rv32ui/xori -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/test/riscv/rv32ui/xori.map build/test/riscv/rv32ui/xori.o build/misc/crt0.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/srai > build/test/riscv/rv32ui/srai.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/srli > build/test/riscv/rv32ui/srli.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/srl > build/test/riscv/rv32ui/srl.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/sub > build/test/riscv/rv32ui/sub.dis\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/xor > build/test/riscv/rv32ui/xor.dis\r\nriscv64-unknown-elf-ld -o build/programs/input2output -O3 -Os -Tbuild/linker_script/turborav.ld -m elf32lriscv -Map=build/programs/input2output.map build/programs/input2output.o /opt/riscv/riscv64-unknown-elf/lib/soft-float/32/no-atomic/libc.a\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/xori > build/test/riscv/rv32ui/xori.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-objdump -DS -M no-aliases -M numeric build/test/riscv/rv32ui/sw > build/test/riscv/rv32ui/sw.dis\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nriscv64-unknown-elf-ld: warning: cannot find entry symbol _crt0; defaulting to 0000000000000000\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nUnrecognized disassembler option: no-aliases\r\nUnrecognized disassembler option: numeric\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/bne --rom build/test/riscv/rv32ui/bne --no-fpga Riscvtest &> build/test/riscv/bne/log.txt || cat build/test/riscv/bne/log.txt; vcd2fst build/test/riscv/bne/Soc.vcd build/test/riscv/bne/wave.fst; rm build/test/riscv/bne/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/remu --rom build/test/riscv/rv32ui/remu --no-fpga Riscvtest &> build/test/riscv/remu/log.txt || cat build/test/riscv/remu/log.txt; vcd2fst build/test/riscv/remu/Soc.vcd build/test/riscv/remu/wave.fst; rm build/test/riscv/remu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/auipc --rom build/test/riscv/rv32ui/auipc --no-fpga Riscvtest &> build/test/riscv/auipc/log.txt || cat build/test/riscv/auipc/log.txt; vcd2fst build/test/riscv/auipc/Soc.vcd build/test/riscv/auipc/wave.fst; rm build/test/riscv/auipc/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/RegBank --rom build/programs/input2output --no-fpga RegBanktest &> build/test/unit/RegBank/log.txt || cat build/test/unit/RegBank/log.txt; vcd2fst build/test/unit/RegBank/RegBank.vcd build/test/unit/RegBank/wave.fst; rm build/test/unit/RegBank/RegBank.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/rem --rom build/test/riscv/rv32ui/rem --no-fpga Riscvtest &> build/test/riscv/rem/log.txt || cat build/test/riscv/rem/log.txt; vcd2fst build/test/riscv/rem/Soc.vcd build/test/riscv/rem/wave.fst; rm build/test/riscv/rem/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/mulhsu --rom build/test/riscv/rv32ui/mulhsu --no-fpga Riscvtest &> build/test/riscv/mulhsu/log.txt || cat build/test/riscv/mulhsu/log.txt; vcd2fst build/test/riscv/mulhsu/Soc.vcd build/test/riscv/mulhsu/wave.fst; rm build/test/riscv/mulhsu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Soc --rom build/programs/input2output --no-fpga Soctest &> build/test/unit/Soc/log.txt || cat build/test/unit/Soc/log.txt; vcd2fst build/test/unit/Soc/Soc.vcd build/test/unit/Soc/wave.fst; rm build/test/unit/Soc/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/xori --rom build/test/riscv/rv32ui/xori --no-fpga Riscvtest &> build/test/riscv/xori/log.txt || cat build/test/riscv/xori/log.txt; vcd2fst build/test/riscv/xori/Soc.vcd build/test/riscv/xori/wave.fst; rm build/test/riscv/xori/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Mult --rom build/programs/input2output --no-fpga Multtest &> build/test/unit/Mult/log.txt || cat build/test/unit/Mult/log.txt; vcd2fst build/test/unit/Mult/Mult.vcd build/test/unit/Mult/wave.fst; rm build/test/unit/Mult/Mult.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/srai --rom build/test/riscv/rv32ui/srai --no-fpga Riscvtest &> build/test/riscv/srai/log.txt || cat build/test/riscv/srai/log.txt; vcd2fst build/test/riscv/srai/Soc.vcd build/test/riscv/srai/wave.fst; rm build/test/riscv/srai/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/bge --rom build/test/riscv/rv32ui/bge --no-fpga Riscvtest &> build/test/riscv/bge/log.txt || cat build/test/riscv/bge/log.txt; vcd2fst build/test/riscv/bge/Soc.vcd build/test/riscv/bge/wave.fst; rm build/test/riscv/bge/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/lh --rom build/test/riscv/rv32ui/lh --no-fpga Riscvtest &> build/test/riscv/lh/log.txt || cat build/test/riscv/lh/log.txt; vcd2fst build/test/riscv/lh/Soc.vcd build/test/riscv/lh/wave.fst; rm build/test/riscv/lh/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/bgeu --rom build/test/riscv/rv32ui/bgeu --no-fpga Riscvtest &> build/test/riscv/bgeu/log.txt || cat build/test/riscv/bgeu/log.txt; vcd2fst build/test/riscv/bgeu/Soc.vcd build/test/riscv/bgeu/wave.fst; rm build/test/riscv/bgeu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/slti --rom build/test/riscv/rv32ui/slti --no-fpga Riscvtest &> build/test/riscv/slti/log.txt || cat build/test/riscv/slti/log.txt; vcd2fst build/test/riscv/slti/Soc.vcd build/test/riscv/slti/wave.fst; rm build/test/riscv/slti/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/jalr --rom build/test/riscv/rv32ui/jalr --no-fpga Riscvtest &> build/test/riscv/jalr/log.txt || cat build/test/riscv/jalr/log.txt; vcd2fst build/test/riscv/jalr/Soc.vcd build/test/riscv/jalr/wave.fst; rm build/test/riscv/jalr/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/srli --rom build/test/riscv/rv32ui/srli --no-fpga Riscvtest &> build/test/riscv/srli/log.txt || cat build/test/riscv/srli/log.txt; vcd2fst build/test/riscv/srli/Soc.vcd build/test/riscv/srli/wave.fst; rm build/test/riscv/srli/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/ForwardingUnit --rom build/programs/input2output --no-fpga ForwardingUnittest &> build/test/unit/ForwardingUnit/log.txt || cat build/test/unit/ForwardingUnit/log.txt; vcd2fst build/test/unit/ForwardingUnit/ForwardingUnit.vcd build/test/unit/ForwardingUnit/wave.fst; rm build/test/unit/ForwardingUnit/ForwardingUnit.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/lui --rom build/test/riscv/rv32ui/lui --no-fpga Riscvtest &> build/test/riscv/lui/log.txt || cat build/test/riscv/lui/log.txt; vcd2fst build/test/riscv/lui/Soc.vcd build/test/riscv/lui/wave.fst; rm build/test/riscv/lui/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/addi --rom build/test/riscv/rv32ui/addi --no-fpga Riscvtest &> build/test/riscv/addi/log.txt || cat build/test/riscv/addi/log.txt; vcd2fst build/test/riscv/addi/Soc.vcd build/test/riscv/addi/wave.fst; rm build/test/riscv/addi/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/ori --rom build/test/riscv/rv32ui/ori --no-fpga Riscvtest &> build/test/riscv/ori/log.txt || cat build/test/riscv/ori/log.txt; vcd2fst build/test/riscv/ori/Soc.vcd build/test/riscv/ori/wave.fst; rm build/test/riscv/ori/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/div --rom build/test/riscv/rv32ui/div --no-fpga Riscvtest &> build/test/riscv/div/log.txt || cat build/test/riscv/div/log.txt; vcd2fst build/test/riscv/div/Soc.vcd build/test/riscv/div/wave.fst; rm build/test/riscv/div/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/sb --rom build/test/riscv/rv32ui/sb --no-fpga Riscvtest &> build/test/riscv/sb/log.txt || cat build/test/riscv/sb/log.txt; vcd2fst build/test/riscv/sb/Soc.vcd build/test/riscv/sb/wave.fst; rm build/test/riscv/sb/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Memory --rom build/programs/input2output --no-fpga Memorytest &> build/test/unit/Memory/log.txt || cat build/test/unit/Memory/log.txt; vcd2fst build/test/unit/Memory/Memory.vcd build/test/unit/Memory/wave.fst; rm build/test/unit/Memory/Memory.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Alu --rom build/programs/input2output --no-fpga Alutest &> build/test/unit/Alu/log.txt || cat build/test/unit/Alu/log.txt; vcd2fst build/test/unit/Alu/Alu.vcd build/test/unit/Alu/wave.fst; rm build/test/unit/Alu/Alu.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/lbu --rom build/test/riscv/rv32ui/lbu --no-fpga Riscvtest &> build/test/riscv/lbu/log.txt || cat build/test/riscv/lbu/log.txt; vcd2fst build/test/riscv/lbu/Soc.vcd build/test/riscv/lbu/wave.fst; rm build/test/riscv/lbu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/sh --rom build/test/riscv/rv32ui/sh --no-fpga Riscvtest &> build/test/riscv/sh/log.txt || cat build/test/riscv/sh/log.txt; vcd2fst build/test/riscv/sh/Soc.vcd build/test/riscv/sh/wave.fst; rm build/test/riscv/sh/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Execute --rom build/programs/input2output --no-fpga Executetest &> build/test/unit/Execute/log.txt || cat build/test/unit/Execute/log.txt; vcd2fst build/test/unit/Execute/Execute.vcd build/test/unit/Execute/wave.fst; rm build/test/unit/Execute/Execute.vcd\r\nscala -classpath build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRav Soc build/synth build/programs/input2output 4 4 True\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/beq --rom build/test/riscv/rv32ui/beq --no-fpga Riscvtest &> build/test/riscv/beq/log.txt || cat build/test/riscv/beq/log.txt; vcd2fst build/test/riscv/beq/Soc.vcd build/test/riscv/beq/wave.fst; rm build/test/riscv/beq/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/mulhu --rom build/test/riscv/rv32ui/mulhu --no-fpga Riscvtest &> build/test/riscv/mulhu/log.txt || cat build/test/riscv/mulhu/log.txt; vcd2fst build/test/riscv/mulhu/Soc.vcd build/test/riscv/mulhu/wave.fst; rm build/test/riscv/mulhu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/lb --rom build/test/riscv/rv32ui/lb --no-fpga Riscvtest &> build/test/riscv/lb/log.txt || cat build/test/riscv/lb/log.txt; vcd2fst build/test/riscv/lb/Soc.vcd build/test/riscv/lb/wave.fst; rm build/test/riscv/lb/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/sra --rom build/test/riscv/rv32ui/sra --no-fpga Riscvtest &> build/test/riscv/sra/log.txt || cat build/test/riscv/sra/log.txt; vcd2fst build/test/riscv/sra/Soc.vcd build/test/riscv/sra/wave.fst; rm build/test/riscv/sra/Soc.vcd\r\n[info] [1.563] // COMPILING < (class TurboRav.Soc)>(10)\r\n[info] [2.225] giving names\r\n[info] [2.587] executing custom transforms\r\n[info] [2.588] convert masked writes of inline mems\r\n[info] [2.870] adding clocks and resets\r\n[info] [2.958] inferring widths\r\n[info] [3.306] checking widths\r\n[info] [3.444] lowering complex nodes to primitives\r\n[info] [3.523] removing type nodes\r\n[info] [3.625] compiling 7055 nodes\r\n[info] [3.625] computing memory ports\r\n[info] [3.760] resolving nodes to the components\r\n[info] [4.255] creating clock domains\r\n[info] [4.297] pruning unconnected IOs\r\n[info] [4.315] checking for unconnected ports\r\n[info] [4.323] checking for combinational loops\r\n[info] [4.419] NO COMBINATIONAL LOOP FOUND\r\n[info] [4.427]  Soc\r\n     apbController\r\n     ravv\r\n         fch\r\n         dec\r\n         exe\r\n             regbank\r\n             alu\r\n             bru\r\n             mult\r\n         mem\r\n         wrb\r\n         fwu\r\n         roam\r\n             rom\r\n             ram\r\n         hdu\r\n     gpio\r\n     dviPeri\r\n         dviTmdsTx\r\n             dvi_tmds_encoder\r\n             dvi_tmds_encoder_1\r\n             dvi_tmds_encoder_2\r\n     TimerPeri\r\n         timer\r\n     TimerPeri_1\r\n         timer\r\n     TimerPeri_2\r\n         timer\r\n     TimerPeri_3\r\n         timer\r\n     TimerPeri_4\r\n         timer\r\n     TimerPeri_5\r\n         timer\r\n\r\n[info] [4.578] COMPILING <apbController (class TurboRav.ApbController)> 0 CHILDREN (0,1)\r\n[info] [4.619] COMPILING <gpio (class TurboRav.Gpio)> 0 CHILDREN (0,1)\r\n[info] [4.624] COMPILING <fch (class TurboRav.Fetch)> 0 CHILDREN (0,2)\r\n[info] [4.628] COMPILING <dec (class TurboRav.Decode)> 0 CHILDREN (0,2)\r\n[info] [4.669] COMPILING <mem (class TurboRav.Memory)> 0 CHILDREN (0,2)\r\n[info] [4.677] COMPILING <wrb (class TurboRav.Writeback)> 0 CHILDREN (0,2)\r\n[info] [4.692] COMPILING <fwu (class TurboRav.ForwardingUnit)> 0 CHILDREN (0,2)\r\n[info] [4.693] COMPILING <hdu (class TurboRav.HazardDetectionUnit)> 0 CHILDREN (0,2)\r\n[info] [4.695] COMPILING <timer (class TurboRav.Timer)> 0 CHILDREN (0,2)\r\n[info] [4.695] COMPILING <timer (class TurboRav.Timer)> 0 CHILDREN (0,2)\r\n[info] [4.696] \t2 components\r\n[info] [4.697] COMPILING <timer (class TurboRav.Timer)> 0 CHILDREN (0,2)\r\n[info] [4.698] \t3 components\r\n[info] [4.698] COMPILING <timer (class TurboRav.Timer)> 0 CHILDREN (0,2)\r\n[info] [4.699] \t4 components\r\n[info] [4.699] COMPILING <timer (class TurboRav.Timer)> 0 CHILDREN (0,2)\r\n[info] [4.700] \t5 components\r\n[info] [4.700] COMPILING <timer (class TurboRav.Timer)> 0 CHILDREN (0,2)\r\n[info] [4.701] \t6 components\r\n[info] [4.701] COMPILING <regbank (class TurboRav.RegBank)> 0 CHILDREN (0,3)\r\n[info] [4.703] COMPILING <alu (class TurboRav.Alu)> 0 CHILDREN (0,3)\r\n[info] [4.705] COMPILING <bru (class TurboRav.BranchUnit)> 0 CHILDREN (0,3)\r\n[info] [4.706] COMPILING <mult (class TurboRav.Mult)> 0 CHILDREN (0,3)\r\n[info] [4.721] COMPILING <rom (class TurboRav.Rom)> 0 CHILDREN (0,3)\r\n[info] [4.724] COMPILING <ram (class TurboRav.FpgaRam)> 0 CHILDREN (0,3)\r\n[info] [4.802] COMPILING <dvi_tmds_encoder (class TurboRav.dvi_tmds_encoder)> 0 CHILDREN (0,3)\r\n[info] [4.871] COMPILING <dvi_tmds_encoder_1 (class TurboRav.dvi_tmds_encoder)> 0 CHILDREN (0,3)\r\n[info] [4.899] \t2 components\r\n[info] [4.900] COMPILING <dvi_tmds_encoder_2 (class TurboRav.dvi_tmds_encoder)> 0 CHILDREN (0,3)\r\n[info] [4.929] \t3 components\r\n[info] [4.929] COMPILING <TimerPeri (class TurboRav.TimerPeri)> 1 CHILDREN (1,1)\r\n[info] [4.935] COMPILING <TimerPeri_1 (class TurboRav.TimerPeri)> 1 CHILDREN (1,1)\r\n[info] [4.937] \t2 components\r\n[info] [4.937] COMPILING <TimerPeri_2 (class TurboRav.TimerPeri)> 1 CHILDREN (1,1)\r\n[info] [4.939] \t3 components\r\n[info] [4.939] COMPILING <TimerPeri_3 (class TurboRav.TimerPeri)> 1 CHILDREN (1,1)\r\n[info] [4.941] \t4 components\r\n[info] [4.941] COMPILING <TimerPeri_4 (class TurboRav.TimerPeri)> 1 CHILDREN (1,1)\r\n[info] [4.943] \t5 components\r\n[info] [4.943] COMPILING <TimerPeri_5 (class TurboRav.TimerPeri)> 1 CHILDREN (1,1)\r\n[info] [4.945] \t6 components\r\n[info] [4.945] COMPILING <exe (class TurboRav.Execute)> 4 CHILDREN (1,2)\r\n[info] [4.970] COMPILING <roam (class TurboRav.Roam)> 2 CHILDREN (1,2)\r\n[info] [4.972] COMPILING <dviTmdsTx (class TurboRav.dvi_tmds_transmitter)> 3 CHILDREN (1,2)\r\n[info] [4.974] COMPILING <ravv (class TurboRav.RavV)> 8 CHILDREN (2,1)\r\n[info] [4.984] COMPILING <dviPeri (class TurboRav.DviPeri)> 1 CHILDREN (2,1)\r\n[info] [4.987] COMPILING <Soc (class TurboRav.Soc)> 10 CHILDREN (3,0)\r\n[warn] TurboRav.scala:21: OUTPUT port io_dec_exe_reg_reads_rs1_valid is unconnected in module  dec in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: OUTPUT port io_dec_exe_reg_reads_rs2_valid is unconnected in module  dec in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: INPUT port io_dec_exe_reg_reads_rs1_valid is unconnected in module  exe in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: INPUT port io_dec_exe_reg_reads_rs2_valid is unconnected in module  exe in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: INPUT port io_enable is unconnected in module  dviTmdsTx in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T2 in <fch (class TurboRav.Fetch)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <fch (class TurboRav.Fetch)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T4 in <fch (class TurboRav.Fetch)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <fch (class TurboRav.Fetch)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T2 in <dec (class TurboRav.Decode)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <dec (class TurboRav.Decode)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_instr in <dec (class TurboRav.Decode)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <dec (class TurboRav.Decode)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T80 in <dec (class TurboRav.Decode)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <dec (class TurboRav.Decode)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_pc in <dec (class TurboRav.Decode)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <dec (class TurboRav.Decode)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*io_dec_exe_reg_reads_rs2_valid in <dec (class TurboRav.Decode)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <dec (class TurboRav.Decode)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*io_dec_exe_reg_reads_rs1_valid in <dec (class TurboRav.Decode)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <dec (class TurboRav.Decode)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T0 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T4 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T6 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T10 in <mem (class TurboRav.Memory)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T14 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T16 in <mem (class TurboRav.Memory)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T18 in <mem (class TurboRav.Memory)>*/ Chisel.UInt(OUTPUT, width=5, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T22 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T24 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T26 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T28 in <mem (class TurboRav.Memory)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T30 in <mem (class TurboRav.Memory)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T32 in <mem (class TurboRav.Memory)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <mem (class TurboRav.Memory)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T1 in <wrb (class TurboRav.Writeback)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T7 in <wrb (class TurboRav.Writeback)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T9 in <wrb (class TurboRav.Writeback)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T13 in <wrb (class TurboRav.Writeback)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T16 in <wrb (class TurboRav.Writeback)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T24 in <wrb (class TurboRav.Writeback)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T32 in <wrb (class TurboRav.Writeback)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T35 in <wrb (class TurboRav.Writeback)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T38 in <wrb (class TurboRav.Writeback)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T40 in <wrb (class TurboRav.Writeback)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <wrb (class TurboRav.Writeback)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T91 in <mult (class TurboRav.Mult)>*/ Chisel.UInt(NODIR, width=0, connect to 0 inputs: ()) IN <mult (class TurboRav.Mult)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T0 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=3, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_exe_ctrl_mult_func in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=3, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T15 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_exe_ctrl_mult_enable in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T24 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=3, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T27 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_imm in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T31 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_exe_ctrl_alu_in_b_sel in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T36 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_exe_ctrl_alu_in_a_sel in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T39 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_pc in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=32, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T43 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=4, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_exe_ctrl_alu_func in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=4, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T48 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=5, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_reg_reads_rs2_bits in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=5, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T51 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_reg_reads_rs2_valid in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T54 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=5, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_reg_reads_rs1_bits in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=5, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T57 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_reg_reads_rs1_valid in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T64 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_wrb_ctrl_sign_extend in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T67 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_wrb_ctrl_is_byte in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T70 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_wrb_ctrl_is_halfword in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T73 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_wrb_ctrl_has_wait_state in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T76 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_wrb_ctrl_rd_sel in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=2, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T80 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_wrb_ctrl_rd_wen in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T84 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_mem_ctrl_is_byte in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T88 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_mem_ctrl_is_halfword in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T92 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_mem_ctrl_read in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T96 in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_mem_ctrl_write in <exe (class TurboRav.Execute)>*/ Chisel.Bool(OUTPUT, width=1, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*T111 in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=5, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\n[warn] TurboRav.scala:21: UNCONNECTED /*flushed_pipeline_rd_addr in <exe (class TurboRav.Execute)>*/ Chisel.UInt(OUTPUT, width=5, connect to 0 inputs: ()) IN <exe (class TurboRav.Execute)> in class TurboRav.TurboRav$\r\nyosys build/synth/Soc.v build/synth/yosys/yosys.ys > build/synth/yosys/yosys.log\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/andi --rom build/test/riscv/rv32ui/andi --no-fpga Riscvtest &> build/test/riscv/andi/log.txt || cat build/test/riscv/andi/log.txt; vcd2fst build/test/riscv/andi/Soc.vcd build/test/riscv/andi/wave.fst; rm build/test/riscv/andi/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/sll --rom build/test/riscv/rv32ui/sll --no-fpga Riscvtest &> build/test/riscv/sll/log.txt || cat build/test/riscv/sll/log.txt; vcd2fst build/test/riscv/sll/Soc.vcd build/test/riscv/sll/wave.fst; rm build/test/riscv/sll/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/BranchUnit --rom build/programs/input2output --no-fpga BranchUnittest &> build/test/unit/BranchUnit/log.txt || cat build/test/unit/BranchUnit/log.txt; vcd2fst build/test/unit/BranchUnit/BranchUnit.vcd build/test/unit/BranchUnit/wave.fst; rm build/test/unit/BranchUnit/BranchUnit.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/add --rom build/test/riscv/rv32ui/add --no-fpga Riscvtest &> build/test/riscv/add/log.txt || cat build/test/riscv/add/log.txt; vcd2fst build/test/riscv/add/Soc.vcd build/test/riscv/add/wave.fst; rm build/test/riscv/add/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/ApbController --rom build/programs/input2output --no-fpga ApbControllertest &> build/test/unit/ApbController/log.txt || cat build/test/unit/ApbController/log.txt; vcd2fst build/test/unit/ApbController/ApbController.vcd build/test/unit/ApbController/wave.fst; rm build/test/unit/ApbController/ApbController.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/slli --rom build/test/riscv/rv32ui/slli --no-fpga Riscvtest &> build/test/riscv/slli/log.txt || cat build/test/riscv/slli/log.txt; vcd2fst build/test/riscv/slli/Soc.vcd build/test/riscv/slli/wave.fst; rm build/test/riscv/slli/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/FpgaRam --rom build/programs/input2output --no-fpga FpgaRamtest &> build/test/unit/FpgaRam/log.txt || cat build/test/unit/FpgaRam/log.txt; vcd2fst build/test/unit/FpgaRam/FpgaRam.vcd build/test/unit/FpgaRam/wave.fst; rm build/test/unit/FpgaRam/FpgaRam.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/bltu --rom build/test/riscv/rv32ui/bltu --no-fpga Riscvtest &> build/test/riscv/bltu/log.txt || cat build/test/riscv/bltu/log.txt; vcd2fst build/test/riscv/bltu/Soc.vcd build/test/riscv/bltu/wave.fst; rm build/test/riscv/bltu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/mulh --rom build/test/riscv/rv32ui/mulh --no-fpga Riscvtest &> build/test/riscv/mulh/log.txt || cat build/test/riscv/mulh/log.txt; vcd2fst build/test/riscv/mulh/Soc.vcd build/test/riscv/mulh/wave.fst; rm build/test/riscv/mulh/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/and --rom build/test/riscv/rv32ui/and --no-fpga Riscvtest &> build/test/riscv/and/log.txt || cat build/test/riscv/and/log.txt; vcd2fst build/test/riscv/and/Soc.vcd build/test/riscv/and/wave.fst; rm build/test/riscv/and/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/or --rom build/test/riscv/rv32ui/or --no-fpga Riscvtest &> build/test/riscv/or/log.txt || cat build/test/riscv/or/log.txt; vcd2fst build/test/riscv/or/Soc.vcd build/test/riscv/or/wave.fst; rm build/test/riscv/or/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/xor --rom build/test/riscv/rv32ui/xor --no-fpga Riscvtest &> build/test/riscv/xor/log.txt || cat build/test/riscv/xor/log.txt; vcd2fst build/test/riscv/xor/Soc.vcd build/test/riscv/xor/wave.fst; rm build/test/riscv/xor/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/divu --rom build/test/riscv/rv32ui/divu --no-fpga Riscvtest &> build/test/riscv/divu/log.txt || cat build/test/riscv/divu/log.txt; vcd2fst build/test/riscv/divu/Soc.vcd build/test/riscv/divu/wave.fst; rm build/test/riscv/divu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/lhu --rom build/test/riscv/rv32ui/lhu --no-fpga Riscvtest &> build/test/riscv/lhu/log.txt || cat build/test/riscv/lhu/log.txt; vcd2fst build/test/riscv/lhu/Soc.vcd build/test/riscv/lhu/wave.fst; rm build/test/riscv/lhu/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/sub --rom build/test/riscv/rv32ui/sub --no-fpga Riscvtest &> build/test/riscv/sub/log.txt || cat build/test/riscv/sub/log.txt; vcd2fst build/test/riscv/sub/Soc.vcd build/test/riscv/sub/wave.fst; rm build/test/riscv/sub/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/lw --rom build/test/riscv/rv32ui/lw --no-fpga Riscvtest &> build/test/riscv/lw/log.txt || cat build/test/riscv/lw/log.txt; vcd2fst build/test/riscv/lw/Soc.vcd build/test/riscv/lw/wave.fst; rm build/test/riscv/lw/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Decode --rom build/programs/input2output --no-fpga Decodetest &> build/test/unit/Decode/log.txt || cat build/test/unit/Decode/log.txt; vcd2fst build/test/unit/Decode/Decode.vcd build/test/unit/Decode/wave.fst; rm build/test/unit/Decode/Decode.vcd\r\narachne-pnr --device 8k --pcf-file build/synth/yosys/icoboard/main.pcf build/synth/yosys/Soc.blif -o build/synth/yosys/icoboard/Soc.asc\r\nseed: 1\r\ndevice: 8k\r\nread_chipdb +/share/arachne-pnr/chipdb-8k.bin...\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/mul --rom build/test/riscv/rv32ui/mul --no-fpga Riscvtest &> build/test/riscv/mul/log.txt || cat build/test/riscv/mul/log.txt; vcd2fst build/test/riscv/mul/Soc.vcd build/test/riscv/mul/wave.fst; rm build/test/riscv/mul/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Timer --rom build/programs/input2output --no-fpga Timertest &> build/test/unit/Timer/log.txt || cat build/test/unit/Timer/log.txt; vcd2fst build/test/unit/Timer/Timer.vcd build/test/unit/Timer/wave.fst; rm build/test/unit/Timer/Timer.vcd\r\n  supported packages: ct256\r\nread_blif build/synth/yosys/Soc.blif...\r\nprune...\r\nread_pcf build/synth/yosys/icoboard/main.pcf...\r\ninstantiate_io...\r\npack...\r\n\r\nAfter packing:\r\nIOs          13 / 206\r\nGBs          0 / 8\r\n  GB_IOs     0 / 8\r\nLCs          3988 / 7680\r\n  DFF        923\r\n  CARRY      692\r\n  CARRY, DFF 0\r\n  DFF PASS   452\r\n  CARRY PASS 51\r\nBRAMs        12 / 32\r\nWARMBOOTs    0 / 1\r\nPLLs         0 / 2\r\n\r\nplace_constraints...\r\npromote_globals...\r\n  promoted clk$2, 947 / 947\r\n  promoted reset$2, 402 / 402\r\n  promoted ravv.fch.T6, 202 / 202\r\n  promoted ravv.mem.T2, 112 / 112\r\n  promoted $auto$dff2dffe.cc:158:make_patterns_logic$15818, 39 / 39\r\n  promoted ravv.fch.exe_fch_branch_taken, 64 / 64\r\n  promoted $auto$dff2dffe.cc:158:make_patterns_logic$21883, 32 / 32\r\n  promoted ravv.dec.T119, 27 / 27\r\n  promoted 8 nets\r\n    3 sr/we\r\n    4 cen/wclke\r\n    1 clk\r\n  8 globals\r\n    3 sr/we\r\n    4 cen/wclke\r\n    1 clk\r\nrealize_constants...\r\n  realized 1\r\nplace...\r\n  initial wire length = 81954\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Writeback --rom build/programs/input2output --no-fpga Writebacktest &> build/test/unit/Writeback/log.txt || cat build/test/unit/Writeback/log.txt; vcd2fst build/test/unit/Writeback/Writeback.vcd build/test/unit/Writeback/wave.fst; rm build/test/unit/Writeback/Writeback.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/dvi_tmds_encoder --rom build/programs/input2output --no-fpga dvi_tmds_encodertest &> build/test/unit/dvi_tmds_encoder/log.txt || cat build/test/unit/dvi_tmds_encoder/log.txt; vcd2fst build/test/unit/dvi_tmds_encoder/dvi_tmds_encoder.vcd build/test/unit/dvi_tmds_encoder/wave.fst; rm build/test/unit/dvi_tmds_encoder/dvi_tmds_encoder.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/dvi_tmds_transmitter --rom build/programs/input2output --no-fpga dvi_tmds_transmittertest &> build/test/unit/dvi_tmds_transmitter/log.txt || cat build/test/unit/dvi_tmds_transmitter/log.txt; vcd2fst build/test/unit/dvi_tmds_transmitter/dvi_tmds_transmitter.vcd build/test/unit/dvi_tmds_transmitter/wave.fst; rm build/test/unit/dvi_tmds_transmitter/dvi_tmds_transmitter.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/sw --rom build/test/riscv/rv32ui/sw --no-fpga Riscvtest &> build/test/riscv/sw/log.txt || cat build/test/riscv/sw/log.txt; vcd2fst build/test/riscv/sw/Soc.vcd build/test/riscv/sw/wave.fst; rm build/test/riscv/sw/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/slt --rom build/test/riscv/rv32ui/slt --no-fpga Riscvtest &> build/test/riscv/slt/log.txt || cat build/test/riscv/slt/log.txt; vcd2fst build/test/riscv/slt/Soc.vcd build/test/riscv/slt/wave.fst; rm build/test/riscv/slt/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/jal --rom build/test/riscv/rv32ui/jal --no-fpga Riscvtest &> build/test/riscv/jal/log.txt || cat build/test/riscv/jal/log.txt; vcd2fst build/test/riscv/jal/Soc.vcd build/test/riscv/jal/wave.fst; rm build/test/riscv/jal/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/blt --rom build/test/riscv/rv32ui/blt --no-fpga Riscvtest &> build/test/riscv/blt/log.txt || cat build/test/riscv/blt/log.txt; vcd2fst build/test/riscv/blt/Soc.vcd build/test/riscv/blt/wave.fst; rm build/test/riscv/blt/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/j --rom build/test/riscv/rv32ui/j --no-fpga Riscvtest &> build/test/riscv/j/log.txt || cat build/test/riscv/j/log.txt; vcd2fst build/test/riscv/j/Soc.vcd build/test/riscv/j/wave.fst; rm build/test/riscv/j/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/unit/Serializer --rom build/programs/input2output --no-fpga Serializertest &> build/test/unit/Serializer/log.txt || cat build/test/unit/Serializer/log.txt; vcd2fst build/test/unit/Serializer/Serializer.vcd build/test/unit/Serializer/wave.fst; rm build/test/unit/Serializer/Serializer.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/simple --rom build/test/riscv/rv32ui/simple --no-fpga Riscvtest &> build/test/riscv/simple/log.txt || cat build/test/riscv/simple/log.txt; vcd2fst build/test/riscv/simple/Soc.vcd build/test/riscv/simple/wave.fst; rm build/test/riscv/simple/Soc.vcd\r\nscala -classpath /mnt/turborav/hw/build/scala/classes/TurboRav.jar:/usr/share/scala/chisel/chisel.jar:/usr/share/java/commons-io/commons-io.jar TurboRav.TurboRavTestRunner --target-directory build/test/riscv/srl --rom build/test/riscv/rv32ui/srl --no-fpga Riscvtest &> build/test/riscv/srl/log.txt || cat build/test/riscv/srl/log.txt; vcd2fst build/test/riscv/srl/Soc.vcd build/test/riscv/srl/wave.fst; rm build/test/riscv/srl/Soc.vcd\r\n  final wire length = 19883\r\ncell = 7957\r\n\r\nAfter placement:\r\nPIOs       15 / 206\r\nPLBs       660 / 960\r\nBRAMs      12 / 32\r\n\r\n  place time 29.78s\r\nroute...\r\n  pass 1, 139 shared.\r\n  pass 2, 58 shared.\r\n  pass 3, 28 shared.\r\n  pass 4, 17 shared.\r\n  pass 5, 14 shared.\r\n  pass 6, 11 shared.\r\n  pass 7, 6 shared.\r\n  pass 8, 3 shared.\r\n  pass 9, 13 shared.\r\n  pass 10, 8 shared.\r\n  pass 11, 1 shared.\r\n  pass 12, 0 shared.\r\n\r\nAfter routing:\r\nspan_4     8409 / 29696\r\nspan_12    1748 / 5632\r\n\r\n  route time 20.86s\r\nwrite_txt build/synth/yosys/icoboard/Soc.asc...\r\nicepack build/synth/yosys/icoboard/Soc.asc build/synth/yosys/icoboard/Soc.bin\r\nicetime -t -p build/synth/yosys/icoboard/main.pcf build/synth/yosys/icoboard/Soc.asc | tee build/synth/yosys/icoboard/icetime.report.txt | tail --lines=4\r\n\r\nTotal number of logic levels: 41\r\nTotal path delay: 45.13 ns (22.16 MHz)\r\n\r\nscons: done building targets.\r\n\r\nreal\t2m35.984s\r\nuser\t13m19.017s\r\nsys\t0m26.123s\r\n"}}