{"push_id":1277712874,"size":24,"distinct_size":24,"ref":"refs/heads/i965-fp64-gen7-scalar-vec4-rc2","head":"6d0c99216075ec04f0bc2742f494988c6ebb1dab","before":"11de28b5bb136a530debedf983c8047af224e7e6","commits":[{"sha":"6ec1f6cd8648ec36ce2183cc81a0e87e990888cb","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: fix scratch reads for 64bit data\n\nv2: Setup for a 64-bit scratch read by checking the type size of the\n    correct register (Iago)","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/6ec1f6cd8648ec36ce2183cc81a0e87e990888cb"},{"sha":"9e9b88e9911e983200b6a899fee1d8a72b7ebd42","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: fix scratch writes for 64bit data\n\nMostly the same stuff as usual: we ned to shuffle the data before we\nwrite and we need to emit two 32-bit write messages (with appropriate\n32-bit writemask channels set) for a full dvec4 scratch write.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/9e9b88e9911e983200b6a899fee1d8a72b7ebd42"},{"sha":"55941073e1226dfb51b9a4615c39a35ca02cb355","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/55941073e1226dfb51b9a4615c39a35ca02cb355"},{"sha":"af5e0ab1a7970c667509f303913794aa7f7cec67","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: fix indentation in move_push_constants_to_pull_constants()","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/af5e0ab1a7970c667509f303913794aa7f7cec67"},{"sha":"c3faefd915f51622bdafdb07ac4c8a59077f7df3","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/c3faefd915f51622bdafdb07ac4c8a59077f7df3"},{"sha":"618aae7c8508e9816a4ed7a6dac7130112095107","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: make emit_pull_constant_load support 64-bit loads\n\nThis way callers don't need to know about 64-bit particularities and\nwe reuse some code.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/618aae7c8508e9816a4ed7a6dac7130112095107"},{"sha":"b268e7f59b853e77daabb1980e1da109df74140c","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: fix store output for 64-bit types\n\nWe need to shuffle the data before it is written to the URB. Also,\ndvec3/4 need two vec4 slots.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/b268e7f59b853e77daabb1980e1da109df74140c"},{"sha":"89b5e2c6ccc812bec664a02ac139c0ce06fe2016","author":{"name":"Samuel Iglesias Gonsálvez","email":"696499febbb821894b47a781ec89e21f5b31e804@igalia.com"},"message":"i965/vec4/gs: fix input loading for 64bit data\n\nv2 (Iago):\n   - Adapt 64-bit path to component packing changes.\n\nSigned-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>\nSigned-off-by: Iago Toral Quiroga <itoral@igalia.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/89b5e2c6ccc812bec664a02ac139c0ce06fe2016"},{"sha":"28ffe932443228a917e7fb18e38426b82816257b","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/tcs: fix input loading for 64-bit data","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/28ffe932443228a917e7fb18e38426b82816257b"},{"sha":"fa9edde01b652c2130dd8d20ab025f2ed4439aa5","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/tcs: fix outputs for 64-bit data","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/fa9edde01b652c2130dd8d20ab025f2ed4439aa5"},{"sha":"7e8fb005e1161346db8fced09f0e5fd1f733a23c","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/tes: fix input loading for 64bit data types","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/7e8fb005e1161346db8fced09f0e5fd1f733a23c"},{"sha":"a1f82bc4ff834b359ef3f9f75acbdbc9a8833f42","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/tes: fix setup_payload() for 64bit data types\n\nUse a width of 2 with 64-bit attributes. Also, if we have a dvec\nsplit across two registers such that components XY are stored in\nthe second half of a register and components ZW are stored in the\nfirst half of the next register, fix up the regioning parameters\nfor channels ZW.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/a1f82bc4ff834b359ef3f9f75acbdbc9a8833f42"},{"sha":"ee8c4e99cf37912d3f18c30b7fdbb6e42cc17ea6","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: split instructions that read 64-bit attrs in TessEval\n\nThe tessellation evaluation stage generates source regions with a vstride=0\nfor these so they hit the gen7 hardware decompression bug. Split them to\nprevent this.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/ee8c4e99cf37912d3f18c30b7fdbb6e42cc17ea6"},{"sha":"9ac6df1cd97c011f845bd9df150099b89574eb65","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: fix writes to Z/W:DF from a FIXED_GRF\n\nThese can happen, for example, in tessellation evaluation when it maps\nincoming attributes to FIXED_GRF registers. In this case, just as with\nVGRFs, we need to make sure we have vstride=0 for these to work.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/9ac6df1cd97c011f845bd9df150099b89574eb65"},{"sha":"c9c1c0cc667e73d5957f359623a68a926a82de85","author":{"name":"Samuel Iglesias Gonsálvez","email":"696499febbb821894b47a781ec89e21f5b31e804@igalia.com"},"message":"i965/vec4: implement force_vstride0 for FIXED_GRF\n\nSigned-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/c9c1c0cc667e73d5957f359623a68a926a82de85"},{"sha":"0d1c5b63123b84e3ffd267f34b2cac30a110f1fc","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: dump subnr for FIXED_GRF\n\nThis came in handy when debugging the payload setup for Tess Eval,\nsince it prints correct subnr for attributes that can be loaded\nin the second half of a register.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/0d1c5b63123b84e3ffd267f34b2cac30a110f1fc"},{"sha":"da8352163c16b7890d26d6766e562d3964bbd81e","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/scalarize_df: do not scalarize instructions with identity swizzles\n\nWe can implement them directly. Also, document other possible improvements\nfor future reference.\n\nv2 (Iago):\n  - Skip checking 32-bit sources.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/da8352163c16b7890d26d6766e562d3964bbd81e"},{"sha":"7340165f399193e95dbbdaebbb9ece94835811b2","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4/scalarize_df: Always scalarize XY / ZW writemasks\n\nNow that we are letting some instructions through without being\nfully scalarized we have to make sure that we do scalarize any\nthat have XY / ZW writemasks, since this don't have native support.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/7340165f399193e95dbbdaebbb9ece94835811b2"},{"sha":"b7747341d55e14d7c8262c2bcac83e10f6df6d4f","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/vec4: enable ARB_gpu_shader_fp64 for Haswell","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/b7747341d55e14d7c8262c2bcac83e10f6df6d4f"},{"sha":"2674508d1e6104a90584fc4c8a6c2bfb66fa904c","author":{"name":"Iago Toral Quiroga","email":"b2aa8582a4b36fb51a36a4a364fccaf9b6512a6d@igalia.com"},"message":"i965/gen7: expose OpenGL 4.0 on Haswell\n\nARB_gpu_shader_fp64 was the last piece missing. Notice that some\nhardware and kernel combinations do not support pipelined register\nwrites, which are required for some OpenGL 4.0 features, in which\ncase the driver won't expose 4.0.","distinct":true,"url":"https://api.github.com/repos/Igalia/mesa/commits/2674508d1e6104a90584fc4c8a6c2bfb66fa904c"}]}
{"actor":{"display_login":"itoral"}}