{"push_id":1396001788,"size":29,"distinct_size":1,"ref":"refs/heads/master","head":"e3c001a750392b1232c304509bb7859f7fc2d8ab","before":"e7832198888a103e0b14a670a488d3ac9a5e5cf3","commits":[{"sha":"54663710442428c009ed4a6ee0e8346ba02865c0","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Experimental 65C02 without dead cycles\n\nChange-Id: Id4cde531512b8c64ba4ec9cf0861a9d827287d49","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/54663710442428c009ed4a6ee0e8346ba02865c0"},{"sha":"b29a092271ef6cda949dacbaea2cbcb0a5825f51","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Added one wait state to ROM accesses to break a long path; meets timing at 64MHz\n\nChange-Id: Ibb142c7c12d116548c838d9104b93029449185c2","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/b29a092271ef6cda949dacbaea2cbcb0a5825f51"},{"sha":"74a91b80739e3fa75aff47cc2a7593ff27a0c29b","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Improved timing on write input to RAM\n\nChange-Id: I333c2c7202f8f06d6e17246deaaca8ea5be8f60d","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/74a91b80739e3fa75aff47cc2a7593ff27a0c29b"},{"sha":"d32e70a645d6e3b4c91e689834125a83dd3d5ef9","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Save one level of logic by enabling RAM all the time\n\nChange-Id: I730cc595dcc8a34d63c8728b6841d13a89b02a5a","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/d32e70a645d6e3b4c91e689834125a83dd3d5ef9"},{"sha":"8637c423642433fe7d83efc3bdefffd1a0d34d3c","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Started adding Arlet's Core - Work In Progress\n\nChange-Id: I168330ca905e1ecf88ffc1af20daff3f33153777","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/8637c423642433fe7d83efc3bdefffd1a0d34d3c"},{"sha":"c97c12990a8c66391a046bd5242fee6c9dc660b7","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Artel's 6502: Fix to allow one wait state on ROM access, meets timing at 80MHz\n\nChange-Id: I2fd25cc21a01e364dd08f1179dbde90eeced8300","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/c97c12990a8c66391a046bd5242fee6c9dc660b7"},{"sha":"d33ee6e93efc5b111eea868c4f0e5e8207b87921","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet core now working at 05/10/20/80MHz\n\nChange-Id: I9718f8cc2af4f4d2da80a0df13a1c3adfcf18143","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/d33ee6e93efc5b111eea868c4f0e5e8207b87921"},{"sha":"3cbfc7fdd7fdcf46d29928d67c1b97390a9d35c0","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Added some additional DCMs\n\nChange-Id: I6cf7c7d5e64af6e8b2b5ffb9966761a7af53493d","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/3cbfc7fdd7fdcf46d29928d67c1b97390a9d35c0"},{"sha":"6246ee6a34232d80a71bdd63a09801256d502817","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement PLX,PHX,PLY,PHY\n\nChange-Id: I2be6895fa6ead45b220b1e00e9db1abf8be4f22d","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/6246ee6a34232d80a71bdd63a09801256d502817"},{"sha":"656f314a94e77d3626409a6d5504b1141ee12848","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement BRA\n\nChange-Id: Ia1fd9b74e315a2f9c488e18a92db0f53d95ab4f7","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/656f314a94e77d3626409a6d5504b1141ee12848"},{"sha":"0b2ea784552497a37a6366f2b8ad3c256fe81f79","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement INC A, DEC A\n\nChange-Id: I1e010164b1c6f964d8d65311ac2487bf770dcd6d","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/0b2ea784552497a37a6366f2b8ad3c256fe81f79"},{"sha":"caed864b5dc9db25fc3abe6bf81d7bd3dc8cbaf0","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement (zp) addressing mode\n\nChange-Id: I321658b78c442fbd1abc50cea72d5ce4478a0052","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/caed864b5dc9db25fc3abe6bf81d7bd3dc8cbaf0"},{"sha":"ba4f10f733a0280ffbae52882430e63d35c03903","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Artel 65C02 WIP: Cosmetic\n\nChange-Id: I23679ce66aa7b0447a9905b170a3a523ddb38632","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/ba4f10f733a0280ffbae52882430e63d35c03903"},{"sha":"13a6233aef549fd00230604a1a3c10a8d14aa623","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement STZ\n\nChange-Id: I233086cc4b88e5c7d235a9e50eada30885a0f0a1","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/13a6233aef549fd00230604a1a3c10a8d14aa623"},{"sha":"756d47004855b48b4594f0b9ebb02742bbecb18b","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement BIT zpx, absx, imm\n\nChange-Id: I78c52c81de2eadf82270a388e74542b491a6a4a6","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/756d47004855b48b4594f0b9ebb02742bbecb18b"},{"sha":"01b2d0ca030126b117e7f8ff984b701d4cb140fb","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement TSB/TXB\n\nChange-Id: Ia9d4de22544dba1fd1d0033bbda60669b59c5360","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/01b2d0ca030126b117e7f8ff984b701d4cb140fb"},{"sha":"8be693f25f9b0f5f54604b027ce8811885609624","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement JMP (,X)\n\nChange-Id: I1c61848b1648d7db9438fd38d1c5f838e566b116","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/8be693f25f9b0f5f54604b027ce8811885609624"},{"sha":"6e0ec32d83285eb2f2ef5bd1d6240e8db5e3c747","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement NOPs (optional)\n\nChange-Id: Ia32355358ef93d35e32567cfeaf51a5a300aeea4","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/6e0ec32d83285eb2f2ef5bd1d6240e8db5e3c747"},{"sha":"66a0e3632d34c1d0358a1854e2ac0fad83548440","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Implement correct 65C02 BCD N/Z flags (optional, disabled)\n\nChange-Id: I2e0b21c87707d5179d7c339d51c342bf3c739d9f","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/66a0e3632d34c1d0358a1854e2ac0fad83548440"},{"sha":"1c6f29a7af351a77536055a5f76a03809d550deb","author":{"name":"David Banks","email":"b4cea4bb99b2bfe98580e8a1404151e1fa946999@hoglet.com"},"message":"Arlet 65C02 WIP: Updated to latest version of Arlet 65c02 from github\n\nChange-Id: Ic18eb4378e9c6c9360d062c06984075b43c943fc","distinct":false,"url":"https://api.github.com/repos/hoglet67/CoPro6502/commits/1c6f29a7af351a77536055a5f76a03809d550deb"}]}
{"actor":{"display_login":"hoglet67"}}