{"push_id":1102438567,"size":15,"distinct_size":15,"ref":"refs/heads/master","head":"c0fdf88ac7cba96db948838325209dd9ee968166","before":"82b3d2dd642265191e09ccd92f24b26e2cb5653a","commits":[{"sha":"aa09aeb5c0e40fdc72538cc3a79620816ad38f3e","author":{"email":"fbe9e45cbb51ebd86366cc402735e3c7e9b1e064@gmail.com","name":"David Majnemer"},"message":"[X86] Promote several single precision FP libcalls on Windows\n\nA number of libcalls don't exist in any particular lib but are, instead,\ndefined in math.h as inline functions (even in C mode!).  Don't rely on\ntheir existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them\ninstead.\n\nN.B. We had logic to handle FREM but were missing out on a number of\nothers.  This change generalizes the FREM handling.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268875 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/aa09aeb5c0e40fdc72538cc3a79620816ad38f3e"},{"sha":"ba60f1665674bed285cb97c8ee8035d8b5d5c081","author":{"email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk","name":"Simon Pilgrim"},"message":"[CostModel][X86] Extended comparison instruction cost model tests to include SSE2/SSE3/SSSE3/SSE41/SSE42 targets\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268877 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/ba60f1665674bed285cb97c8ee8035d8b5d5c081"},{"sha":"ba458cf29fa616520132a3caad3b83495c868681","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[X86] Remove extra patterns that check for BUILD_VECTOR of all 0s. These are always canonicalized to v4i32/v8i32/v16i32 except for in SSE1 only when only v4f32 is supported.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268880 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/ba458cf29fa616520132a3caad3b83495c868681"},{"sha":"2b1f6c23bcbd88f5e7a3d6659446e45c9592cedf","author":{"email":"2ca028346d1d172bdf6d5bd55544812ec8ee16e2@gmail.com","name":"Bruno Cardoso Lopes"},"message":"[Bitcode] Fix an unsigned integer overflow while parsing bitcode wrapper header\n\nSpecially crafted bitcode wrapper headers can cause unsigned interger\noverflow and lead to crashes when wrapping around. Fix the offset check\nand avoid such scenarios.\n\nWriting a testcase for this would involve editing the binary to generate\nvalues that trigger the overflow, since this would never happen while\ngenerating the bitcode in regular compilation flows, so there's\ncurrently no feasible way add one.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268881 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/2b1f6c23bcbd88f5e7a3d6659446e45c9592cedf"},{"sha":"79c01a2d3ede1c8f57f7760aea2c6964bd9dfe0a","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"Remove Windows line endings in some tests to prepare for a future commit. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268882 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/79c01a2d3ede1c8f57f7760aea2c6964bd9dfe0a"},{"sha":"605a46a88d23962288023fb2a2ae6eafe6b1b7e1","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[X86] Re-generate tests using update_llc_test_checks.py to prepare for a future commit. NFC\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268883 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/605a46a88d23962288023fb2a2ae6eafe6b1b7e1"},{"sha":"dba67a4fdb6b7b7dce9b959b6d7d2963b1c642b6","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268884 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/dba67a4fdb6b7b7dce9b959b6d7d2963b1c642b6"},{"sha":"5cb772fb8a0a5e5ae56db833bbac451b75521207","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[AVX512] Change predicates on some vXi16/vXi8 AVX store patterns so they stay enabled unless VLX and BWI instructions are supported.\"\n\nWithout this we could fail instruction selection if VLX was enabled, but BWI wasn't.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268885 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/5cb772fb8a0a5e5ae56db833bbac451b75521207"},{"sha":"f453dfba6fbcbf4c8ff717105ea0162ee62841ba","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[AVX512] Add missing patterns for non-temporal stores of 128/256-bit vXi8/vXi16/vXi32 when VLX is enabled. The equivalent AVX1/2 patterns are disabled by VLX.\n\nThis caused regular stores to be emitted instead.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268886 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/f453dfba6fbcbf4c8ff717105ea0162ee62841ba"},{"sha":"328324434e13a7ac23c5d3fb01e4a9e51ea7c1ba","author":{"email":"b54130faddcfc8b1a37f55f2f3b8b3dc057ccb2e@samsung.com","name":"Junmo Park"},"message":"Minor code cleanups. NFC.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268888 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/328324434e13a7ac23c5d3fb01e4a9e51ea7c1ba"},{"sha":"84a0ca551ea48b662283f12bb1c79c8d9a8d8b5c","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[AVX512] Add non-temporal store patterns for v16i32/v32i16/v64i8.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268889 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/84a0ca551ea48b662283f12bb1c79c8d9a8d8b5c"},{"sha":"437f2fc22e4645b16b999a943af87658d5968f63","author":{"email":"47bc6657766d30b03d03ddcf00c3effaee52e71a@apple.com","name":"Mehdi Amini"},"message":"ThinLTOCodeGenerator: ignore 0 values for the cache settings.\n\nFrom: Mehdi Amini <mehdi.amini@apple.com>\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268890 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/437f2fc22e4645b16b999a943af87658d5968f63"},{"sha":"63eccc2eca676b6e0a6b28dbc70fd6626b429fb3","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268891 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/63eccc2eca676b6e0a6b28dbc70fd6626b429fb3"},{"sha":"3c29a695f2bd5c0a9872330140d529288b4037fc","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[X86] Strengthen some type contraints for floating point round and extend.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268892 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/3c29a695f2bd5c0a9872330140d529288b4037fc"},{"sha":"c0fdf88ac7cba96db948838325209dd9ee968166","author":{"email":"35327c1aec5e90bdd5db37fe08c7aa0a48abe398@apple.com","name":"Frederic Riss"},"message":"[dsymutil] Fix -arch option for thumb variants.\n\nr267249 removed the dual ARM/Thumb interface from MachOObjectFile,\nsimplifying llvm-dsymutil's code. This unfortunately also regressed\nllvm-dsymutil's ability to select thumb slices, because the simplified\ncode was also dealing with the discrepency between the slice arch\n(eg. armv7m) and the triple arch name (eg. thumbv7m).\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268894 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/Microsoft/llvm/commits/c0fdf88ac7cba96db948838325209dd9ee968166"}]}