{"push_id":1088056915,"size":1,"distinct_size":1,"ref":"refs/heads/upstream","head":"fa0eab1450bffc9c2eae932aa92edb4f12d662da","before":"dc030335547e38363acd34b3440db3ff0d6bd9b6","commits":[{"sha":"fa0eab1450bffc9c2eae932aa92edb4f12d662da","author":{"email":"af4b1a06dcc93e086b35435d5654eb2aff59399a@redking.me.uk","name":"Simon Pilgrim"},"message":"[InstCombine][SSE] Add MOVMSK support to SimplifyDemandedUseBits\n\nThe MOVMSK instructions copies a vector elements' sign bits to the low bits of a scalar register and zeros the high bits.\n\nThis patch adds MOVMSK support to SimplifyDemandedUseBits so that its aware that the upper bits are known to be zero. It also removes the call to MOVMSK if none of the lower bits are actually required and just returns zero.\n\nDifferential Revision: http://reviews.llvm.org/D19614\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@267873 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/rendering-io/LLVM/commits/fa0eab1450bffc9c2eae932aa92edb4f12d662da"}]}