{"action":"created","issue":{"url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/137","repository_url":"https://api.github.com/repos/UCSBarchlab/PyRTL","labels_url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/137/labels{/name}","comments_url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/137/comments","events_url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/137/events","html_url":"https://github.com/UCSBarchlab/PyRTL/issues/137","id":151473708,"number":137,"title":"Input and Output shared between blocks","user":{"login":"abe-k","id":4240556,"avatar_url":"https://avatars.githubusercontent.com/u/4240556?v=3","gravatar_id":"","url":"https://api.github.com/users/abe-k","html_url":"https://github.com/abe-k","followers_url":"https://api.github.com/users/abe-k/followers","following_url":"https://api.github.com/users/abe-k/following{/other_user}","gists_url":"https://api.github.com/users/abe-k/gists{/gist_id}","starred_url":"https://api.github.com/users/abe-k/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/abe-k/subscriptions","organizations_url":"https://api.github.com/users/abe-k/orgs","repos_url":"https://api.github.com/users/abe-k/repos","events_url":"https://api.github.com/users/abe-k/events{/privacy}","received_events_url":"https://api.github.com/users/abe-k/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":10,"created_at":"2016-04-27T19:43:05Z","updated_at":"2016-05-04T03:45:26Z","closed_at":null,"body":"To avoid needing `io_map` and the contortions involved in mapping interfaces between pre- and post-synthesis blocks, we agreed in the meeting to make Input and Output WireVectors be shareable between blocks, so that pre- and post-synthesis blocks could have the same connections.\r\n\r\nThe major problem is that currently, WireVectors store a reference to the block they belong to, and use that reference when creating LogicNets. Rather than specializing just Input and Output to (somehow) not need to reference a specific block, would it be reasonable to make all WireVectors simply use the working block for construction? (Still having the sanity check only allow I/O to be shared.) If not, how should existing in multiple blocks be handled?"},"comment":{"url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/comments/216734583","html_url":"https://github.com/UCSBarchlab/PyRTL/issues/137#issuecomment-216734583","issue_url":"https://api.github.com/repos/UCSBarchlab/PyRTL/issues/137","id":216734583,"user":{"login":"abe-k","id":4240556,"avatar_url":"https://avatars.githubusercontent.com/u/4240556?v=3","gravatar_id":"","url":"https://api.github.com/users/abe-k","html_url":"https://github.com/abe-k","followers_url":"https://api.github.com/users/abe-k/followers","following_url":"https://api.github.com/users/abe-k/following{/other_user}","gists_url":"https://api.github.com/users/abe-k/gists{/gist_id}","starred_url":"https://api.github.com/users/abe-k/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/abe-k/subscriptions","organizations_url":"https://api.github.com/users/abe-k/orgs","repos_url":"https://api.github.com/users/abe-k/repos","events_url":"https://api.github.com/users/abe-k/events{/privacy}","received_events_url":"https://api.github.com/users/abe-k/received_events","type":"User","site_admin":false},"created_at":"2016-05-04T03:45:26Z","updated_at":"2016-05-04T03:45:26Z","body":"To summarize the conclusions of today's meeting on this: all WireVectors will remain tied to single blocks, but simulation tracing will be indexed by name rather than identity, as Input and Output names will remain the same after synthesis. This access-by-name will also apply to memories. To make the change easier, `.trace` will still allow access by identity, but issue a deprecation warning when it occurs.\r\n\r\nWe do still need to decide how to handle specifying initial values for registers in synthesis. (By name would make sense, but synthesis has split them into automatically-named single-bit registers.)"}}