{"action":"created","comment":{"url":"https://api.github.com/repos/martinisgroup/servers/pulls/comments/48688551","id":48688551,"diff_hunk":"@@ -0,0 +1,505 @@\n+# Ethernet Commands for GHzDAC\n+\n+John Martinis\n+\n+\n+## Revision History\n+\n+### Code for GHzDAC, version 3 of FPGA\n+\n+Ethernet commands have Preamble, Destination, and Source fields that are automatically included with the driver module.\n+For SequenceV1, two basic commands are possible: (1) SRAM Write or (2) Register Write for control of the sequencer.\n+These two commands are recognized according to the value of the first two length bytes, given below, which gives the total number of bytes of the following data field `d(1)..d(length)`.\n+In general, ethernet packets can have data-field lengths from 46 to 1500.\n+\n+MAC address of card is `0.1.202.170.0.(00sw)` (i.e. `00:01:CA:AA:00:..`), where `sw[5..0]` is the dipswitch value on the board with `on=0`.\n+\n+Check I2C lines if need to add resistor for slow slew rate.\n+\n+* `LED[0]` light indicates FPGA 250MHz PLL not locked\n+* `LED[1]` light indicates external 1 GHz PLL not locked (or not programmed)\n+* `LED[3]` light is latched of notlocked internal 1GHzDAC serializer PLL\n+\n+* `mon[0]` is pulsed high for 4 ns at beginning of SRAM sequence (for triggering).\n+* `mon[1]` is 250 MHz clock\n+\n+The data in SRAM is streamed 4 bytes each ns to the DAC converters and ECL output.\n+\n+\n+### V4; May 24, 2008\n+\n+* Added bit for 0 or 1 page of memory, set by `start[7]` bit\n+* `MEMadrstart[15..8]` set to 0 or 1 to define page of mem write.\n+* Issac’s output: `mon[1]` set to serial0.\n+* Fix: start resets MemAdr to 0 in AddressControl, always restarts sequence.\n+* All phases on LVDS set to 90 degrees.\n+* Software-build constant set to 5. Program files: GHzDAC_V4_S5\n+* Added 2nd block of SRAM (2048 ns) to present memory (8192 ns).\n+  Write to new SRAM with addresses corresponding to times 8192 to 8192+2048-1 ns.\n+  For readout, the address of this 2nd block is offset by `SRAMoffset[7..0]`*1024 ns.\n+  When reading addresses in this offset range, the previous SRAM value is output.\n+\n+\n+### GHzDAC_V5\n+\n+* Added comments on daisychain\n+* Add idle=3 to Master/Slave mode\n+* 16 bits for start delay; d(52) from spare to `startdelay[15..8]`\n+* sram_big module for larger FPGA\n+* Software-build constant set to 8 for big FPGA EPS30F484.\n+  Software-build constant set to 7 for small FPGA EP2S15F484.\n+\n+\n+### GHzDAC_V6\n+\n+Various test programs\n+\n+\n+### GHzDAC_V7\n+\n+* Add counter for SRAM trigger\n+* Add its readback register\n+* `mon[0]=sram` started\n+* `mon[1]=sramtrig` (now counted)\n+* Software-build constant set to 12 for big FPGA EPS30F484.\n+  Software-build constant set to 11 for small FPGA EP2S15F484.\n+\n+\n+### GHzDAC_V8; April 2013\n+\n+This is a major revision. Changes are:\n+\n+1. Take out memsequence code, just replacing it with immediate SRAM call\n+   with a repeating call after a programmable delay.\n+   There is now no output on the Ethernet generated from the memsequence timer.\n+2. Pass 16 measurement signals via two Daisychain lines UP the chain.\n+   Note that master start command passes timing pulse DOWN the chain.\n+3. Include JumpTable for repeated sequences and conditional jumps.\n+   SRAMoffset and multiblock removed since can use counter and jumps for delay.\n+4. Idles at end address after SRAM sequence.\n+5. Start command coded differently, with no slave register, to make more clear.\n+6. Register write selects output monitors, `mon[0]` and `mon[1]`.\n+7. Register output counters for SRAMstart, SRAMend, 2 JumpIndex values\n+8. Software-build constant set to 13 for small FPGA EP2S15F484.\n+   Software-build constant set to 14 for big FPGA EP2S30F484.\n+\n+\n+## SRAM Write:\n+\n+Writes into SRAM (now on FPGA) a total of 256 words (each 32 bits long, 4 bytes).\n+\n+Starting at address `sram(+0) = (adrstart[20..8],00000000)`, and ending at `sram(+255) = (adrstart[20..8],11111111)`.\n+\n+Each group of 256 words is referred to as a “derp.”\n+\n+The data is streamed 1 word (32 bits / 4 bytes) per ns into the DAC converters and ECL outputs.\n+LVDS serializers stream 4 words per clock cycle at 250 MHz (4ns).\n+\n+NOTE: lowest two bits of SRAMstart set to [00] and SRAMend set to [11] in present version of software to simplify serialization code.\n+\n+Normal memory block is 8K SRAM words, or 5 bits of `adrstart[12..8]`.\n+This gives 8 us of programming (but see Multi-block function below).\n+Each word has the following format:\n+\n+    DACA[13..0]  = bits[13..0]    For D/A converter A output\n+    DACB[13..0]  = bits[27..14]   ForD/A converter B output\n+    SERIAL[3..0] = bits[31..28]   For ECL serial output\n+\n+The full SRAM Write packet is as follows:\n+\n+    l(1)  length[15..8]   set to 4; ( length[15..0]= 256*4+2=1026 )\n+    l(2)  length[7..0]    set to 2\n+\n+    d(1)  adrstart[15..8]   Page for start address: middle bits,\n+    d(2)  adrstart[23..16]  upper bits; size of SRAM implies bits [23..19] = 0\n+\n+    d(3)  sram(+0)[7..0]    Writes bits [7..0]   at address [adrstart[23..8],0]\n+    d(4)  sram(+0)[15..8]   Writes bits [15..8]  at address [adrstart[23..8],0]\n+    d(5)  sram(+0)[23..16]  Writes bits [23..16] at address [adrstart[23..8],0]\n+    d(6)  sram(+0)[31..24]  Writes bits [31..24] at address [adrstart[23..8],0]\n+\n+    d(7)  sram(+1)[7..0]    Writes bits [7..0]   at address [adrstart[23..8],1]\n+    d(8)  sram(+1)[15..8]   Writes bits [15..8]  at address [adrstart[23..8],1]\n+    d(9)  sram(+1)[23..16]  Writes bits [23..16] at address [adrstart[23..8],1]\n+    d(10) sram(+1)[31..24]  Writes bits [31..24] at address [adrstart[23..8],1]\n+    ...\n+    d(1023) sram(+255)[7..0]    Writes bits [7..0]   at address [adrstart[23..8],255]\n+    d(1024) sram(+255)[15..8]   Writes bits [15..8]  at address [adrstart[23..8],255]\n+    d(1025) sram(+255)[23..16]  Writes bits [23..16] at address [adrstart[23..8],255]\n+    d(1026) sram(+255)[31..24]  Writes bits [31..24] at address [adrstart[23..8],255]\n+\n+\n+## JumpTable Write:\n+\n+This similar to memory write for memsequencer, but now it loads in data for jumptable.\n+The data consists of 16 bytes of CountTo counter limits and 64*8 bytes of Jumptable entries.\n+\n+fromAddr and toAddr are addresses of 4ns blocks. If we set StartAdr `d(17..19)` to 0 and a jump table END with FromAdr=10, SRAM will run for 10*4ns=40ns before hitting the END command.\n+\n+    l(1)  length[15..8]   set to 2  (528 = 16+64*8)\n+    l(2)  length[7..0]    set to 16\n+\n+    d(1)  CountTo0[7..0]  CountTo0[31..0] is maximum count of counter 0\n+    d(2)  CountTo0[15..8]\n+    d(3)  CountTo0[23..16]\n+    d(4)  CountTo0[31..24]\n+\n+    d(5)  CountTo1[7..0]  CountTo1[31..0] is for counter 1\n+    ...\n+    d(16) CountTo3[7..0]  CountTo3[31..0] is for counter 3\n+\n+    d(17) StartAdr[7..0]    3 bytes for StartAdr[23..0]\n+    d(18) StartAdr[15..8]\n+    d(19) StartAdr[23..16]\n+    d(20) StartAdr[7..0]    Must be equal to d(17),d(18),d(19)\n+    d(21) StartAdr[15..8]\n+    d(22) StartAdr[23..16]\n+    d(23) StartOpCode[7..0]  =5 for NOP\n+    d(24) StartOpCode[15..8] =0\n+\n+    d(25) FromAdr(1)[7..0]  3 bytes for FromAdr(1)[23..0]-1, jumptable index=1\n+    d(26) FromAdr(1)[15..8]\n+    d(27) FromAdr(1)[23.16]\n+    d(28) ToAdr(1)[7..0]    3 bytes for ToAdr(1)[23..0]\n+    d(29) ToAdr(1)[15..8]\n+    d(30) ToAdr(1)[23.16]\n+    d(32) OpCode(1)[7..0]   2 bytes for OpCode(1)[15..0]\n+    d(32) OpCode(1)[15..8]\n+\n+    d(33) FromAdr(2)[7..0]  Bytes for FromAdr(2)[23..0]-1, index=2\n+    ...\n+    d(528) OpCode(63)[15..8] Bytes for OpCode(63)[15..8], index=63\n+\n+\n+### Operation codes for JumpTable:\n+\n+    dddddddd ddddddd0   IDLE: extra d[14..0] 4ns clocks (max 128 us)\n+                          (2**15)-1 *4ns = 131068ns\n+                          Does this mean minimum idle time is 2*4ns = 8ns?\n+                          Is the lowest order bit ignored or what? Maybe lowest bit=0 indicates IDLE.\n+\n+    xxjjjjjj iiiin001   CHECK: if daisychain bit(index=iiii) = n\n+                          T:          jump ToAdr, load JumpIndex jjjjjj\n+                          F:          AdrCounter+1,    JumpIndex+1\n+\n+    xxjjjjjj xxxx1101   JUMP:         jump ToAdr, load JumpIndex jjjjjj\n+\n+    xxxxxxxx xxxx0101   NOP:          AdrCounter+1,    JumpIndex+1\n+\n+    xxjjjjjj xxccx011   CYCLE: until count(ind=cc) = CountTo(ind=cc)\n+                          F: count+1, jump ToAdr, load JumpIndex jjjjjj\n+                          T: count=0, AdrCounter+1,    JumpIndex+1\n+\n+    xxxxxxxx xxxxx111   END: SRAMend, stops Adr counting at FromAdr+2\n+\n+    x=do not care.\n+\n+JumpTable addresses FromAdr must be 1 less than actual address (due to pipelining).\n+For StartAdr (index=0 of JumpTable), set FromAdr and ToAdr to actual address.\n+For END, set FromAdr to 2 less than actual stop address, where Adr will idles.\n+ToAdr is actual value.\n+\n+`CHECK` evaluated at address FromAdr+1\n+\n+`IDLE` produces d+1 clock cycles at address FromAdr+1. (ToAdr not used in IDLE) setting to 0 (`dd...dd=0`) produces 1 clock cycle of delay for the instruction itself.","path":"fpgalib/docs/GHzDAC_v8.md","position":204,"original_position":204,"commit_id":"b408d3e73396cc724196775b4bf0c37c92a4f471","original_commit_id":"b408d3e73396cc724196775b4bf0c37c92a4f471","user":{"login":"DanielSank","id":4584456,"avatar_url":"https://avatars.githubusercontent.com/u/4584456?v=3","gravatar_id":"","url":"https://api.github.com/users/DanielSank","html_url":"https://github.com/DanielSank","followers_url":"https://api.github.com/users/DanielSank/followers","following_url":"https://api.github.com/users/DanielSank/following{/other_user}","gists_url":"https://api.github.com/users/DanielSank/gists{/gist_id}","starred_url":"https://api.github.com/users/DanielSank/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/DanielSank/subscriptions","organizations_url":"https://api.github.com/users/DanielSank/orgs","repos_url":"https://api.github.com/users/DanielSank/repos","events_url":"https://api.github.com/users/DanielSank/events{/privacy}","received_events_url":"https://api.github.com/users/DanielSank/received_events","type":"User","site_admin":false},"body":"The punctuation in this paragraph is a bit off in a few places. Give it a once-over.","created_at":"2016-01-02T23:06:05Z","updated_at":"2016-01-02T23:06:05Z","html_url":"https://github.com/martinisgroup/servers/pull/283#discussion_r48688551","pull_request_url":"https://api.github.com/repos/martinisgroup/servers/pulls/283","_links":{"self":{"href":"https://api.github.com/repos/martinisgroup/servers/pulls/comments/48688551"},"html":{"href":"https://github.com/martinisgroup/servers/pull/283#discussion_r48688551"},"pull_request":{"href":"https://api.github.com/repos/martinisgroup/servers/pulls/283"}}},"pull_request":{"url":"https://api.github.com/repos/martinisgroup/servers/pulls/283","id":52899649,"html_url":"https://github.com/martinisgroup/servers/pull/283","diff_url":"https://github.com/martinisgroup/servers/pull/283.diff","patch_url":"https://github.com/martinisgroup/servers/pull/283.patch","issue_url":"https://api.github.com/repos/martinisgroup/servers/issues/283","number":283,"state":"open","locked":false,"title":"Add markdown version of documentation for GHz DACs","user":{"login":"maffoo","id":129268,"avatar_url":"https://avatars.githubusercontent.com/u/129268?v=3","gravatar_id":"","url":"https://api.github.com/users/maffoo","html_url":"https://github.com/maffoo","followers_url":"https://api.github.com/users/maffoo/followers","following_url":"https://api.github.com/users/maffoo/following{/other_user}","gists_url":"https://api.github.com/users/maffoo/gists{/gist_id}","starred_url":"https://api.github.com/users/maffoo/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/maffoo/subscriptions","organizations_url":"https://api.github.com/users/maffoo/orgs","repos_url":"https://api.github.com/users/maffoo/repos","events_url":"https://api.github.com/users/maffoo/events{/privacy}","received_events_url":"https://api.github.com/users/maffoo/received_events","type":"User","site_admin":false},"body":"We already have markdown version of the ADC docs, this adds it for the DACs as well. For now, I've just copied the content and done some simple markdown formatting. I have not yet changed the packet descriptions to be zero-indexed, as was done for the ADC docs. For all of our sanity we should do that before merging, but for now I'd like reviewers to just look at the basic formatting and compare the content to what's in the word doc. I'll make a separate change to fix the indexing.","created_at":"2015-12-07T20:57:13Z","updated_at":"2016-01-02T23:06:05Z","closed_at":null,"merged_at":null,"merge_commit_sha":"95866cfc6d88de62b2d14a8f79427bc08e271fb0","assignee":null,"milestone":null,"commits_url":"https://api.github.com/repos/martinisgroup/servers/pulls/283/commits","review_comments_url":"https://api.github.com/repos/martinisgroup/servers/pulls/283/comments","review_comment_url":"https://api.github.com/repos/martinisgroup/servers/pulls/comments{/number}","comments_url":"https://api.github.com/repos/martinisgroup/servers/issues/283/comments","statuses_url":"https://api.github.com/repos/martinisgroup/servers/statuses/b408d3e73396cc724196775b4bf0c37c92a4f471","head":{"label":"martinisgroup:u/maffoo/dac-docs","ref":"u/maffoo/dac-docs","sha":"b408d3e73396cc724196775b4bf0c37c92a4f471","user":{"login":"martinisgroup","id":5026004,"avatar_url":"https://avatars.githubusercontent.com/u/5026004?v=3","gravatar_id":"","url":"https://api.github.com/users/martinisgroup","html_url":"https://github.com/martinisgroup","followers_url":"https://api.github.com/users/martinisgroup/followers","following_url":"https://api.github.com/users/martinisgroup/following{/other_user}","gists_url":"https://api.github.com/users/martinisgroup/gists{/gist_id}","starred_url":"https://api.github.com/users/martinisgroup/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/martinisgroup/subscriptions","organizations_url":"https://api.github.com/users/martinisgroup/orgs","repos_url":"https://api.github.com/users/martinisgroup/repos","events_url":"https://api.github.com/users/martinisgroup/events{/privacy}","received_events_url":"https://api.github.com/users/martinisgroup/received_events","type":"Organization","site_admin":false},"repo":{"id":21184808,"name":"servers","full_name":"martinisgroup/servers","owner":{"login":"martinisgroup","id":5026004,"avatar_url":"https://avatars.githubusercontent.com/u/5026004?v=3","gravatar_id":"","url":"https://api.github.com/users/martinisgroup","html_url":"https://github.com/martinisgroup","followers_url":"https://api.github.com/users/martinisgroup/followers","following_url":"https://api.github.com/users/martinisgroup/following{/other_user}","gists_url":"https://api.github.com/users/martinisgroup/gists{/gist_id}","starred_url":"https://api.github.com/users/martinisgroup/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/martinisgroup/subscriptions","organizations_url":"https://api.github.com/users/martinisgroup/orgs","repos_url":"https://api.github.com/users/martinisgroup/repos","events_url":"https://api.github.com/users/martinisgroup/events{/privacy}","received_events_url":"https://api.github.com/users/martinisgroup/received_events","type":"Organization","site_admin":false},"private":false,"html_url":"https://github.com/martinisgroup/servers","description":"LabRAD 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