{"push_id":1180274554,"size":4,"distinct_size":4,"ref":"refs/heads/master","head":"7323fa718dfa38036bcae3854ce364a9471f5763","before":"bea4300957d7b9c0bdd69e337a510f5dfa07bb22","commits":[{"sha":"d52a8fdf7646d489a38c32ef01ef0821cb7b3d38","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[CodeGen] Make ShuffleVectorSDNode::commuteMask take a MutableArrayRef instead of SmallVectorImpl. NFC.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274095 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/d52a8fdf7646d489a38c32ef01ef0821cb7b3d38"},{"sha":"b4a751197815389ce3ace3497f8153eada68a922","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[DAGCombine] Add test cases to show that DAG combining an OR of two shuffles with zero vectors doesn't work if the zero vector is the first operand of the shuffle. Fix coming in a follow up patch.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274096 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/b4a751197815389ce3ace3497f8153eada68a922"},{"sha":"f1bcc5ea2c0c958a2e403fcc2926ba151f0fff44","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[DAGCombine] Teach DAG combine to handle ORs of shuffles involving zero vectors where the zero vector is the first operand to the shuffle instead of the second.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274097 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/f1bcc5ea2c0c958a2e403fcc2926ba151f0fff44"},{"sha":"7323fa718dfa38036bcae3854ce364a9471f5763","author":{"name":"Craig Topper","email":"6a75d0b5116f69c017582fb3bf52b5bed0a243c0@gmail.com"},"message":"[ValueTracking] Teach computeKnownBits for PHI nodes to compute sign bit for a recurrence with a NSW addition.\n\nIf a operation for a recurrence is an addition with no signed wrap and both input sign bits are 0, then the result sign bit must also be 0. Similar for the negative case.\n\nI found this deficiency while playing around with a loop in the x86 backend that contained a signed division that could be optimized into an unsigned division if we could prove both inputs were positive. One of them being the loop induction variable. With this patch we can perform the conversion for this case. One of the test cases here is a contrived variation of the loop I was looking at.\n\nDifferential revision: http://reviews.llvm.org/D21493\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274098 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/earl/llvm-mirror/commits/7323fa718dfa38036bcae3854ce364a9471f5763"}]}
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