{"action":"opened","issue":{"url":"https://api.github.com/repos/funningboy/uvm_axi/issues/3","repository_url":"https://api.github.com/repos/funningboy/uvm_axi","labels_url":"https://api.github.com/repos/funningboy/uvm_axi/issues/3/labels{/name}","comments_url":"https://api.github.com/repos/funningboy/uvm_axi/issues/3/comments","events_url":"https://api.github.com/repos/funningboy/uvm_axi/issues/3/events","html_url":"https://github.com/funningboy/uvm_axi/issues/3","id":132937857,"number":3,"title":"[proposed Label] Question","user":{"login":"josefoelias","id":17175809,"avatar_url":"https://avatars.githubusercontent.com/u/17175809?v=3","gravatar_id":"","url":"https://api.github.com/users/josefoelias","html_url":"https://github.com/josefoelias","followers_url":"https://api.github.com/users/josefoelias/followers","following_url":"https://api.github.com/users/josefoelias/following{/other_user}","gists_url":"https://api.github.com/users/josefoelias/gists{/gist_id}","starred_url":"https://api.github.com/users/josefoelias/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/josefoelias/subscriptions","organizations_url":"https://api.github.com/users/josefoelias/orgs","repos_url":"https://api.github.com/users/josefoelias/repos","events_url":"https://api.github.com/users/josefoelias/events{/privacy}","received_events_url":"https://api.github.com/users/josefoelias/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2016-02-11T10:38:06Z","updated_at":"2016-02-11T10:38:06Z","closed_at":null,"body":"Hi, \r\nI am trying to get your code work with my VHDL project (AXI MASTER), but I'm not familiar with Verilog. \r\nI'm working in Vivado on school project and I need validate that my IP core works before I am testing it on HW.\r\n\r\nI need one AXI slave (with memory if its possible) and test write read with my core. \r\n \r\nIf I understand it, I need to generate BFM with Phyton and then declare+instantiate it in my vhdl. But which files I need to generate ? \r\n\r\nThanks, Josef "}}