{"push_id":1222217147,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"5f4b4c42964445d1bc517c461090f17655e84131","before":"7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b","commits":[{"sha":"ae738acdc5f02d232e035538c67d63ba19b9ccaa","author":{"name":"Lee Leahy","email":"998fcc69fdbe3b90f118b5047a29482122ca0b32@intel.com"},"message":"cpu/x86: Support CPUs without rdmsr/wrmsr instructions\n\nQuark does not support the rdmsr and wrmsr instructions.  In this case\nuse a SOC specific routine to support the setting of the MTRRs.  Migrate\nthe code from FSP 1.1 to be x86 CPU common.\n\nSince all rdmsr/wrmsr accesses are being converted, fix the build\nfailure for quark in lib/reg_script.c.  Move the soc_msr_x routines and\ntheir depencies from romstage/mtrr.c to reg_access.c.\n\nTEST=Build and run on Galileo Gen2\n\nChange-Id: Ibc68e696d8066fbe2322f446d8c983d3f86052ea\nSigned-off-by: Lee Leahy <leroy.p.leahy@intel.com>\nReviewed-on: https://review.coreboot.org/15839\nTested-by: build bot (Jenkins)\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/ae738acdc5f02d232e035538c67d63ba19b9ccaa"},{"sha":"5f4b4c42964445d1bc517c461090f17655e84131","author":{"name":"Lee Leahy","email":"998fcc69fdbe3b90f118b5047a29482122ca0b32@intel.com"},"message":"arch/x86: Add bootblock and postcar support for SOC MTRR access\n\nQuark does not support the rdmsr and wrmsr instructions.  Use SOC\nspecific routines to configure the MTRRs on Quark based platforms.\nAdd cpu_common.c as a build dependency to provide access to the routine\ncpu_phys_address_size.\n\nTEST=Build and run on Galileo Gen2\n\nChange-Id: I43b7067c66c5c55b42097937e862078adf17fb19\nSigned-off-by: Lee Leahy <leroy.p.leahy@intel.com>\nReviewed-on: https://review.coreboot.org/15846\nTested-by: build bot (Jenkins)\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/5f4b4c42964445d1bc517c461090f17655e84131"}]}
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