{"action":"opened","issue":{"url":"https://api.github.com/repos/tuura/scenco/issues/2","labels_url":"https://api.github.com/repos/tuura/scenco/issues/2/labels{/name}","comments_url":"https://api.github.com/repos/tuura/scenco/issues/2/comments","events_url":"https://api.github.com/repos/tuura/scenco/issues/2/events","html_url":"https://github.com/tuura/scenco/issues/2","id":129134530,"number":2,"title":"Add technology mapping support ","user":{"login":"snowleopard","id":675286,"avatar_url":"https://avatars.githubusercontent.com/u/675286?v=3","gravatar_id":"","url":"https://api.github.com/users/snowleopard","html_url":"https://github.com/snowleopard","followers_url":"https://api.github.com/users/snowleopard/followers","following_url":"https://api.github.com/users/snowleopard/following{/other_user}","gists_url":"https://api.github.com/users/snowleopard/gists{/gist_id}","starred_url":"https://api.github.com/users/snowleopard/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/snowleopard/subscriptions","organizations_url":"https://api.github.com/users/snowleopard/orgs","repos_url":"https://api.github.com/users/snowleopard/repos","events_url":"https://api.github.com/users/snowleopard/events{/privacy}","received_events_url":"https://api.github.com/users/snowleopard/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2016-01-27T12:54:49Z","updated_at":"2016-01-27T12:54:49Z","closed_at":null,"body":"See https://github.com/tuura/scenco/blob/master/TechnologyMapping.hs#L7-L8.\r\n\r\nCurrent idea: ask logic synthesis tool like `ABC` to synthesise a bunch of boolean functions into a circuit and export it in Verilog/VHDL format."}}