{"action":"closed","issue":{"url":"https://api.github.com/repos/m-labs/artiq/issues/502","repository_url":"https://api.github.com/repos/m-labs/artiq","labels_url":"https://api.github.com/repos/m-labs/artiq/issues/502/labels{/name}","comments_url":"https://api.github.com/repos/m-labs/artiq/issues/502/comments","events_url":"https://api.github.com/repos/m-labs/artiq/issues/502/events","html_url":"https://github.com/m-labs/artiq/issues/502","id":164191946,"number":502,"title":"Rule violation when trying to generate bitstream for qc2","user":{"login":"r-srinivas","id":11219276,"avatar_url":"https://avatars.githubusercontent.com/u/11219276?v=3","gravatar_id":"","url":"https://api.github.com/users/r-srinivas","html_url":"https://github.com/r-srinivas","followers_url":"https://api.github.com/users/r-srinivas/followers","following_url":"https://api.github.com/users/r-srinivas/following{/other_user}","gists_url":"https://api.github.com/users/r-srinivas/gists{/gist_id}","starred_url":"https://api.github.com/users/r-srinivas/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/r-srinivas/subscriptions","organizations_url":"https://api.github.com/users/r-srinivas/orgs","repos_url":"https://api.github.com/users/r-srinivas/repos","events_url":"https://api.github.com/users/r-srinivas/events{/privacy}","received_events_url":"https://api.github.com/users/r-srinivas/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":2,"created_at":"2016-07-06T22:44:37Z","updated_at":"2016-07-07T06:57:50Z","closed_at":"2016-07-07T06:57:50Z","body":"\r\nI was trying to generate the bitstream for the release-1 branch (commit 07b41763c20ac7470d723d8e30e937adb0250ac9) and ran into the following error,\r\n\r\n```\r\nERROR: [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 12. For example, the following two ports in this bank have conflicting VCCOs:  \r\nuser_sma_gpio_n (LVCMOS25, requiring VCCO=2.500) and dds_d[0] (LVTTL, requiring VCCO=3.300)\r\n```\r\n\r\nThis results in an oserror later,\r\n\r\n```\r\nERROR: [Common 17-39] 'place_design' failed due to earlier errors.\r\n\r\n    while executing\r\n\"place_design\"\r\n    (file \"top.tcl\" line 99)\r\n```\r\n\r\nThat was from `vivado.log`. On the terminal I see,\r\n\r\n```\r\nERROR: [Common 17-39] 'place_design' failed due to earlier errors.\r\n\r\n    while executing\r\n\"place_design\"\r\n    (file \"top.tcl\" line 99)\r\nINFO: [Common 17-206] Exiting Vivado at Wed Jul  6 16:25:06 2016...\r\nTraceback (most recent call last):\r\n  File \"/home/rabi/anaconda3/lib/python3.5/runpy.py\", line 184, in _run_module_as_main\r\n    \"__main__\", mod_spec)\r\n  File \"/home/rabi/anaconda3/lib/python3.5/runpy.py\", line 85, in _run_code\r\n    exec(code, run_globals)\r\n  File \"/home/rabi/artiq-dev-1.1/artiq/artiq/gateware/targets/kc705.py\", line 408, in <module>\r\n    main()\r\n  File \"/home/rabi/artiq-dev-1.1/artiq/artiq/gateware/targets/kc705.py\", line 404, in main\r\n    build_artiq_soc(soc, builder_argdict(args))\r\n  File \"/home/rabi/artiq-dev-1.1/artiq/artiq/gateware/soc.py\", line 61, in build_artiq_soc\r\n    builder.build()\r\n  File \"/home/rabi/artiq-dev-1.1/misoc/misoc/integration/builder.py\", line 156, in build\r\n    run=self.compile_gateware, **kwargs)\r\n  File \"/home/rabi/artiq-dev-1.1/misoc/misoc/integration/soc_core.py\", line 195, in build\r\n    self.platform.build(self, *args, **kwargs)\r\n  File \"/home/rabi/artiq-dev-1.1/migen/migen/build/xilinx/platform.py\", line 28, in build\r\n    return self.toolchain.build(self, *args, **kwargs)\r\n  File \"/home/rabi/artiq-dev-1.1/migen/migen/build/xilinx/vivado.py\", line 131, in build\r\n    _run_vivado(build_name, toolchain_path, source)\r\n  File \"/home/rabi/artiq-dev-1.1/migen/migen/build/xilinx/vivado.py\", line 70, in _run_vivado\r\n    raise OSError(\"Subprocess failed\")\r\nOSError: Subprocess failed\r\n```\r\n\r\nHow can I fix this? I've attached the vivado.log file if that's useful.\r\n\r\n[vivado_log.txt](https://github.com/m-labs/artiq/files/351052/vivado_log.txt)\r\n\r\n"}}
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