{"action":"created","issue":{"url":"https://api.github.com/repos/machinekit/mksocfpga/issues/9","repository_url":"https://api.github.com/repos/machinekit/mksocfpga","labels_url":"https://api.github.com/repos/machinekit/mksocfpga/issues/9/labels{/name}","comments_url":"https://api.github.com/repos/machinekit/mksocfpga/issues/9/comments","events_url":"https://api.github.com/repos/machinekit/mksocfpga/issues/9/events","html_url":"https://github.com/machinekit/mksocfpga/issues/9","id":148437793,"number":9,"title":"Support Sensible Firmware Names & Multiple Configurations","user":{"login":"cdsteinkuehler","id":1993109,"avatar_url":"https://avatars.githubusercontent.com/u/1993109?v=3","gravatar_id":"","url":"https://api.github.com/users/cdsteinkuehler","html_url":"https://github.com/cdsteinkuehler","followers_url":"https://api.github.com/users/cdsteinkuehler/followers","following_url":"https://api.github.com/users/cdsteinkuehler/following{/other_user}","gists_url":"https://api.github.com/users/cdsteinkuehler/gists{/gist_id}","starred_url":"https://api.github.com/users/cdsteinkuehler/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cdsteinkuehler/subscriptions","organizations_url":"https://api.github.com/users/cdsteinkuehler/orgs","repos_url":"https://api.github.com/users/cdsteinkuehler/repos","events_url":"https://api.github.com/users/cdsteinkuehler/events{/privacy}","received_events_url":"https://api.github.com/users/cdsteinkuehler/received_events","type":"User","site_admin":false},"labels":[{"url":"https://api.github.com/repos/machinekit/mksocfpga/labels/problem","name":"problem","color":"c5def5"}],"state":"closed","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":48,"created_at":"2016-04-14T17:57:45Z","updated_at":"2016-08-06T20:39:54Z","closed_at":"2016-08-06T20:39:54Z","body":"The generated bit file for all current projects is named \"soc_system.rbf\", which will rapidly cause problems once more than one person is using this code on a single board.  The Mesanet firmware, for example, not only has different firmware builds for each physical FPGA platform, but also several 'flavors' of the firmware depending on which daughter cards are connected.\r\n\r\nFor example, the 5i25 (which Michael Brown based the initial DE0-Nano configuration on) has at least 14 different bit files (7i74x2.bit, 7i76_7i74.bit, etc).\r\n\r\nI have started work on an expansion card for the DE0-Nano which could potentially support up to four DB25 connectors.  When combined with the various daughter cards available from Mesa, this makes a *LOT* of firmware permutations!  We need to think about how to keep this from causing mass confusion, and how to make it easy to build custom firmware configurations (either upon request, or hopefully easy enough so actual users could do it)."},"comment":{"url":"https://api.github.com/repos/machinekit/mksocfpga/issues/comments/238047640","html_url":"https://github.com/machinekit/mksocfpga/issues/9#issuecomment-238047640","issue_url":"https://api.github.com/repos/machinekit/mksocfpga/issues/9","id":238047640,"user":{"login":"cdsteinkuehler","id":1993109,"avatar_url":"https://avatars.githubusercontent.com/u/1993109?v=3","gravatar_id":"","url":"https://api.github.com/users/cdsteinkuehler","html_url":"https://github.com/cdsteinkuehler","followers_url":"https://api.github.com/users/cdsteinkuehler/followers","following_url":"https://api.github.com/users/cdsteinkuehler/following{/other_user}","gists_url":"https://api.github.com/users/cdsteinkuehler/gists{/gist_id}","starred_url":"https://api.github.com/users/cdsteinkuehler/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/cdsteinkuehler/subscriptions","organizations_url":"https://api.github.com/users/cdsteinkuehler/orgs","repos_url":"https://api.github.com/users/cdsteinkuehler/repos","events_url":"https://api.github.com/users/cdsteinkuehler/events{/privacy}","received_events_url":"https://api.github.com/users/cdsteinkuehler/received_events","type":"User","site_admin":false},"created_at":"2016-08-06T20:39:54Z","updated_at":"2016-08-06T20:39:54Z","body":"I'm considering this resolved and closing the issue.  We no longer use the same generic name for all FPGA bit files, and it is possible to support multiple hardware configurations (and the corresponding bitfiles) on the same FPGA platform.  See the DE0_Nano_SoC_DB25 configurations for working examples.\r\n\r\nWe will likely want to create additional configurations and possible rename some project files for consistency, but these can be their own issue if needed.  The basic problem of using one \"magic\" name for the FPGA bitfile which prompted me to create this issue has been resolved for some time."}}
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