{"push_id":1161915727,"size":5,"distinct_size":0,"ref":"refs/heads/ti-u-boot-2016.05-next","head":"f5b8c9939a20a698377cb0410330408a6e460fe7","before":"ec04b98dd5d65789faa09349bd684be2ccaab1bc","commits":[{"sha":"23952029bbd00ed1418c13fb256532ebaccbf18b","author":{"name":"Lokesh Vutla","email":"d569bcfb48ad30e36af736a1b765de6031c428c4@ti.com"},"message":"arch: arm: omap: Declare size of ddr very early\n\nDeclare the size of ddr very early in spl, so that this can be\nused to enable cache.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>","distinct":false,"url":"https://api.github.com/repos/rcn-ee/ti-uboot/commits/23952029bbd00ed1418c13fb256532ebaccbf18b"},{"sha":"8790c0394a430c4c1edbc5b22e2207f67d70fc78","author":{"name":"Michal Simek","email":"056004c1ed9f4370020018a5c4660566aa9371c0@xilinx.com"},"message":"spl: Introduce new function spl_board_prepare_for_boot\n\nCall this function before passing control from SPL.\nFor fpga case it is necessary to enable for example level shifters\nwhen bitstream is programmed.\n\nSigned-off-by: Michal Simek <michal.simek@xilinx.com>\nReviewed-by: Simon Glass <sjg@chromium.org>","distinct":false,"url":"https://api.github.com/repos/rcn-ee/ti-uboot/commits/8790c0394a430c4c1edbc5b22e2207f67d70fc78"},{"sha":"847a68eeecfc64915b2c90b2d05d43b031ab508b","author":{"name":"Lokesh Vutla","email":"d569bcfb48ad30e36af736a1b765de6031c428c4@ti.com"},"message":"spl: reorder the assignment of board info to global data\n\nMove the assignment of board info to global data a bit early which is safe,\nso that ram details can be used to enable caches.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>","distinct":false,"url":"https://api.github.com/repos/rcn-ee/ti-uboot/commits/847a68eeecfc64915b2c90b2d05d43b031ab508b"},{"sha":"6f80053c773e50a6591d5dec3fb88d3e7f8cc1ee","author":{"name":"Lokesh Vutla","email":"d569bcfb48ad30e36af736a1b765de6031c428c4@ti.com"},"message":"spl: Add support for enabling dcache\n\nEnabling dcache in spl.\n\nSigned-off-by: Lokesh Vutla <lokeshvutla@ti.com>","distinct":false,"url":"https://api.github.com/repos/rcn-ee/ti-uboot/commits/6f80053c773e50a6591d5dec3fb88d3e7f8cc1ee"},{"sha":"f5b8c9939a20a698377cb0410330408a6e460fe7","author":{"name":"Praneeth Bajjuri","email":"5fbc980950c6a03fdd58d441eb2d6475d7b9eae4@ti.com"},"message":"driver: qspi: correct QSPI disable CS reset value\n\nCorrecting QSPI disable/unselect CS reset value.\nCTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8]\n\nThis is not causing any issue, but its better\nto untouch the reserved bits.\n\nReviewed-by: Mugunthan V N <mugunthanvnm@ti.com>\nSigned-off-by: Praneeth Bajjuri <praneeth@ti.com>\nSigned-off-by: Ravi Babu <ravibabu@ti.com>","distinct":false,"url":"https://api.github.com/repos/rcn-ee/ti-uboot/commits/f5b8c9939a20a698377cb0410330408a6e460fe7"}]}
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