{"push_id":1368596805,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"3bfe3404df32ca226c624be0435c640bf1ebeae7","before":"ffb3a2d22506a86e205a757029f60abccfef0486","commits":[{"sha":"3bfe3404df32ca226c624be0435c640bf1ebeae7","author":{"name":"Furquan Shaikh","email":"2de1ca671c2aecd43854ec4189fa53a4e08008e8@chromium.org"},"message":"intel/skylake: Add support to enable wake-on-usb attach/detach\n\nThree things are required to enable wake-on-usb:\n1. 5V to USB ports should be enabled in S3.\n2. ASL file needs to have appropriate wake bit set.\n3. XHCI controller should have the wake on attach/detach bit set for the\ncorresponding port in PORTSCN register.\n\nOnly part missing was #3.\n\nThis CL adds support to allow mainboard to define a bitmap in\ndevicetree corresponding to the ports that it wants to enable\nwake-on-usb feature. Based on the bitmap, wake on attach/detach bits in\nPORTSCN would be set by xhci.asl for the appropriate ports.\n\nBUG=chrome-os-partner:58734\nBRANCH=None\nTEST=Verified that with port 5 enabled, chell wakes up from S3 on usb\nattach/detach.\n\nChange-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf\nSigned-off-by: Furquan Shaikh <furquan@chromium.org>\nReviewed-on: https://review.coreboot.org/17056\nTested-by: build bot (Jenkins)\nReviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>\nReviewed-by: Aaron Durbin <adurbin@chromium.org>","distinct":true,"url":"https://api.github.com/repos/coreboot/coreboot/commits/3bfe3404df32ca226c624be0435c640bf1ebeae7"}]}
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