{"action":"created","comment":{"url":"https://api.github.com/repos/libopencm3/libopencm3/pulls/comments/74843632","id":74843632,"diff_hunk":"@@ -0,0 +1,897 @@\n+/** @defgroup dsi_defines DSI Defines\n+ *\n+ * @ingroup STM32F4xx_defines\n+ *\n+ * @brief Defined Constants and Macros for the STM32F4xx DSI Peripheral\n+ *\n+ * @version 1.0.0\n+ *\n+ * @date 7 July 2016\n+ *\n+ * LGPL License Terms @ref lgpl_license\n+ */\n+\n+/*\n+ * STM32F4 DSI Host Defines\n+ *\n+ * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com>\n+ *\n+ * This file is part of the libopencm3 project.\n+ *\n+ * This library is free software: you can redistribute it and/or modify\n+ * it under the terms of the GNU Lesser General Public License as published by\n+ * the Free Software Foundation, either version 3 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This library is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n+ * GNU Lesser General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU Lesser General Public License\n+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.\n+ *\n+ */\n+\n+#include <libopencm3/cm3/common.h>\n+#include <libopencm3/stm32/memorymap.h>\n+\n+#ifndef DSI_H\n+#define DSI_H\n+\n+/**@{*/\n+\n+/**\n+ *\t@brief Macro for reading register bitfields\n+ *\n+ *\tThis macro will extract the bit field value from the named\n+ *\tREGISTER and the named FIELD. The value in X is assumed to\n+ *\tcome from the register. The field value is returned shifted\n+ *\tright into the least significant bits.\n+ *\n+ *\t@param[in] reg The data sheet register name\n+ *\t@param[in] field The data sheet bit field name\n+ *\t@param[in] x A value from that register.\n+ *\n+ *\t**Example:**\n+ *\n+ * \\code{.c}\n+ *\tuint32_t x = DSI_GHCR;\n+ *\tuint8_t data0 = DSI_GET(GHCR, DATA0, x);\n+ * \\endcode\n+ *\n+ * You could also extract directly from GHCR with this code:\n+ *\n+ * \\code{.c}\n+ *\tuint8_t data0 = DSI_GET(GHCR, DATA0, DSI_GHCR);\n+ * \\endcode\n+ *\n+ */\n+#define DSI_GET(reg, field, x) \\\n+    (((x) >> DSI_ ## reg ## _ ## field ##_SHIFT) & DSI_ ## reg ##_ ## field ##_MASK)\n+\n+/**\n+ * \t@brief Macros for setting  register bitfields\n+ * \n+ * \tThis macro will insert the bit field value passed as X\n+ * \tinto position for the named REGISTER and the named FIELD.\n+ * \tThe macro returns a 32 bit integer with the field value\n+ * \tmasked and shifted into position.\n+ * \n+ * \t@param[in] reg The data sheet register name\n+ * \t@param[in] field The data sheet bit field name\n+ * \t@param[in] x A value to insert into that register\n+ * \n+ * \t**Example:**\n+ * \n+ *\tIt is useful when ORing together multiple fields.\n+ * \\code{.c}\n+ * \tDSI_GHCR = DSI_SET(GHCR, DATA0, 0x22) | DSI_SET(GHCR, DATA1, 0x35);\n+ * \\endcode\n+ *\n+ * Or when you have an existing register and want to just update a field:\n+ *\n+ * \\code{.c}\n+ * \tDSI_CCR |= DSI_SET(CCR, TOCKDIV, 05);\n+ * \\endcode\n+ *\n+ */\n+#define DSI_SET(reg, field, x) \\\n+    (((x) & DSI_ ## reg ##_## field ##_MASK) << DSI_## reg ##_## field ##_SHIFT)\n+\n+/**\n+ *\t@brief Macros for masking register bitfields\n+ *\n+ *\tThis macro will create a mask (all 1 bits) which can be\n+ *\tused to clear (when inverted) the bits of the bit field\n+ *\tnamed FIELD in the data sheet of the register named REGISTER\n+ *\tin the data sheet.\n+ *\n+ *\t@param[in] reg The data sheet register name\n+ *\t@param[in] field The data sheet bit field name\n+ *\n+ *\t**Example:**\n+ *\n+ *\tClear the `DATA0` and `DATA1` fields of the `GHCR` register:\n+ *\n+ *\t\\code{.c}\n+ * \tDSI_GHCR &= ~(DSI_MASK(GHCR, DATA0) | DSI_MASK(GHCR, DATA1);\n+ * \\endcode\n+ *\n+ */\n+#define DSI_MASK(reg, field) \\\n+    ((DSI_ ## reg ##_## field ##_MASK) << DSI_## reg ##_## field ##_SHIFT)\n+\n+/*\n+ * DSI Host Version Register\n+ */\n+#define DSI_VR\t\t\t\tMMIO32(DSI_BASE + 0x0U)\t\n+\n+/*\n+ * DSI Host Control Register\n+ */\n+#define DSI_CR\t\t\t\tMMIO32(DSI_BASE + 0x4U)\n+#define DSI_CR_EN\t\t\t(1 << 0)\n+\n+/*\n+ * DSI Host Clock Control Register\n+ */\n+#define DSI_CCR\t\t\t\tMMIO32(DSI_BASE + 0x8U)\n+#define DSI_CCR_TOCKDIV_SHIFT\t\t8\n+#define DSI_CCR_TOCKDIV_MASK\t\t0xff\n+#define DSI_CCR_TXECKDIV_SHIFT\t\t0\n+#define DSI_CCR_TXECKDIV_MASK\t\t0xff\n+\n+/*\n+ * DSI Host LTDC VCID Register\n+ */\n+#define DSI_LVCIDR\t\t\tMMIO32(DSI_BASE + 0xcU)\n+#define DSI_LVCIDR_VCID_SHIFT\t\t0\n+#define DSI_LVCIDR_VCID_MASK\t\t0x3\n+\n+/*\n+ * DSI Host LTDC Color Coding Register\n+ */\n+#define DSI_LCOLCR\t\t\tMMIO32(DSI_BASE + 0x10U)\n+#define DSI_LCOLCR_LPE\t\t\t(1 << 8)\n+#define DSI_LCOLCR_COLC_SHIFT\t\t0\n+#define DSI_LCOLCR_COLC_MASK\t\t0xf\n+\n+/*\n+ * DSI Host LTDC Polarity Configuration Register\n+ */\n+#define DSI_LPCR\t\t\tMMIO32(DSI_BASE + 0x14U)\n+#define DSI_LPCR_HSP\t\t\t(1 << 2)\n+#define DSI_LPCR_VSP\t\t\t(1 << 1)\n+#define DSI_LPCR_DEP\t\t\t(1 << 0)\n+\n+/*\n+ * DSI Host Low-power Configuration Register\n+ */\n+#define DSI_LPMCR\t\t\tMMIO32(DSI_BASE + 0x18U)\n+#define DSI_LPMCR_LPSIZE_SHIFT\t\t16\n+#define DSI_LPMCR_LPSIZE_MASK\t\t0xff\n+#define DSI_LPMCR_VLPSIZE_SHIFT\t\t0\n+#define DSI_LPMCR_VLPSIZE_MASK\t\t0xff\n+\n+/*\n+ * DSI Host Protocol Configuration Register\n+ */\n+#define DSI_PCR\t\t\t\tMMIO32(DSI_BASE + 0x2cU)\n+#define DSI_PCR_CRCRXE\t\t\t(1 << 4)\n+#define DSI_PCR_ECCRXE\t\t\t(1 << 3)\n+#define DSI_PCR_BTAE\t\t\t(1 << 2)\n+#define DSI_PCR_ETRXE\t\t\t(1 << 1)\n+#define DSI_PCR_ETTXE\t\t\t(1 << 0)\n+\n+/*\n+ * DSI Host Generic VCID Register\n+ */\n+#define DSI_GVCIDR\t\t\tMMIO32(DSI_BASE + 0x30U)\n+#define DSI_GVCIDR_VCID_SHIFT\t\t0\n+#define DSI_GVCIDR_VCID_MASK\t\t0x3\n+\n+/*\n+ * DSI Host mode Configuration Register\n+ */\n+#define DSI_MCR\t\t\t\tMMIO32(DSI_BASE + 0x34U)\n+#define DSI_MCR_CMDM\t\t\t(1 << 0)\n+\n+/*\n+ * DSI Host Video mode Configuration Register\n+ */\n+#define DSI_VMCR\t\t\tMMIO32(DSI_BASE + 0x38U)\n+#define DSI_VMCR_PGO\t\t\t(1 << 24)\n+#define DSI_VMCR_PGM\t\t\t(1 << 20)\n+#define DSI_VMCR_PGE\t\t\t(1 << 16)\n+#define DSI_VMCR_LPCE\t\t\t(1 << 15)\n+#define DSI_VMCR_FBTAAE\t\t\t(1 << 14)\n+#define DSI_VMCR_LPHFE\t\t\t(1 << 13)\n+#define DSI_VMCR_LPHBPE\t\t\t(1 << 12)\n+#define DSI_VMCR_LPVAE\t\t\t(1 << 11)\n+#define DSI_VMCR_LPVFPE\t\t\t(1 << 10)\n+#define DSI_VMCR_LPVBPE\t\t\t(1 << 9)\n+#define DSI_VMCR_LPVSAE\t\t\t(1 << 8)\n+#define DSI_VMCR_VMT_SHIFT\t\t0\n+#define DSI_VMCR_VMT_MASK\t\t0x3\n+#define DSI_VMCR_VMT_NON_BURST_PULSE\t0x0\n+#define DSI_VMCR_VMT_NON_BURSE_EVENT\t0x1\n+#define DSI_VMCR_VMT_BURST\t\t0x2\n+\n+/*\n+ * DSI Host Video Packet Configuration Register\n+ */\n+#define DSI_VPCR\t\t\tMMIO32(DSI_BASE + 0x3CU)\n+#define DSI_VPCR_VPSIZE_SHIFT\t\t0\n+#define DSI_VPCR_VPSIZE_MASK\t\t0x3fff\n+\n+/*\n+ * DSI Host Video Chunks Configuration Register\n+ */\n+#define DSI_VCCR\t\t\tMMIO32(DSI_BASE + 0x40U)\n+#define DSI_VCCR_NUMC_SHIFT\t\t0\n+#define DSI_VCCR_NUMC_MASK\t\t0x1fff\n+\n+/*\n+ * DSI Host Video Null Packet Configuration Register\n+ */\n+#define DSI_VNPCR\t\t\tMMIO32(DSI_BASE + 0x44U)\n+#define DSI_VNPCR_NPSIZE_SHIFT\t\t0\n+#define DSI_VNPCR_NPSIZE_MASK\t\t0x1fff\n+\n+/*\n+ * DSI Host Video HSA Configuration Register\n+ */\n+#define DSI_VHSACR\t\t\tMMIO32(DSI_BASE + 0x48U)\n+#define DSI_VHSACR_HSA_SHIFT\t\t0\n+#define DSI_VHSACR_HSA_MASK\t\t0xfff\n+\n+/*\n+ * DSI Host Video HBP Configuration Register\n+ */\n+#define DSI_VHBPCR\t\t\tMMIO32(DSI_BASE + 0x4CU)\n+#define DSI_VHBPCR_HBP_SHIFT\t\t0\n+#define DSI_VHBPCR_HBP_MASK\t\t0xfff\n+\n+/*\n+ * DSI Host Video Line Configuration Register\n+ */\n+#define DSI_VLCR\t\t\tMMIO32(DSI_BASE + 0x50U)\n+#define DSI_VLCR_HLINE_SHIFT\t\t0\n+#define DSI_VLCR_HLINE_MASK\t\t0x7fff\n+\n+/*\n+ * DSI Host Video VSA Configuration Register\n+ */\n+#define DSI_VVSACR\t\t\tMMIO32(DSI_BASE + 0x54U)\n+#define DSI_VVSACR_VSA_SHIFT\t\t0\n+#define DSI_VVSACR_VSA_MASK\t\t0x3ff\n+\n+/*\n+ * DSI Host Video VBP Configuration Register\n+ */\n+#define DSI_VVBPCR\t\t\tMMIO32(DSI_BASE + 0x58U)\n+#define DSI_VVBPCR_VBP_SHIFT\t\t0\n+#define DSI_VVBPCR_VBP_MASK\t\t0x3ff\n+\n+/*\n+ * DSI Host Video VFP Configuration Register\n+ */\n+#define DSI_VVFPCR\t\t\tMMIO32(DSI_BASE + 0x5CU)\n+#define DSI_VVFPCR_VFP_SHIFT\t\t0\n+#define DSI_VVFPCR_VFP_MASK\t\t0x3ff\n+\n+/*\n+ * DSI Host Video VA Configuration Register\n+ */\n+#define DSI_VVACR\t\t\tMMIO32(DSI_BASE + 0x60U)\n+#define DSI_VVACR_VA_SHIFT\t\t0\n+#define DSI_VVACR_VA_MASK\t\t0x3fff\n+\n+/*\n+ * DSI Host LTDC Command Configuration Register\n+ */\n+#define DSI_LCCR\t\t\tMMIO32(DSI_BASE + 0x64U)\n+#define DSI_LCCR_CMDSIZE_SHIFT\t\t0\n+#define DSI_LCCR_CMDSIZE_MASK\t\t0xffff\n+\n+/*\n+ * DSI Host Command mode Configuration Register\n+ */\n+#define DSI_CMCR\t\t\tMMIO32(DSI_BASE + 0x68U)\n+#define DSI_CMCR_MRDPS\t\t\t(1 << 24)\n+#define DSI_CMCR_DLWTX\t\t\t(1 << 19)\n+#define DSI_CMCR_DSR0TX\t\t\t(1 << 18)\n+#define DSI_CMCR_DSW1TX\t\t\t(1 << 17)\n+#define DSI_CMCR_DSW0TX\t\t\t(1 << 16)\n+/* Bit 15 reserved */\n+#define DSI_CMCR_GLWTX\t\t\t(1 << 14)\n+#define DSI_CMCR_GSR2TX\t\t\t(1 << 13)\n+#define DSI_CMCR_GSR1TX\t\t\t(1 << 12)\n+#define DSI_CMCR_GSR0TX\t\t\t(1 << 11)\n+#define DSI_CMCR_GSW2TX\t\t\t(1 << 10)\n+#define DSI_CMCR_GSW1TX\t\t\t(1 << 9)\n+#define DSI_CMCR_GSW0TX\t\t\t(1 << 8)\n+/* Bits 7:2 Reserved */\n+#define DSI_CMCR_ARE\t\t\t(1 << 1)\n+#define DSI_CMCR_TEARE\t\t\t(1 << 0)\n+\n+/*\n+ * DSI Host Generic Header Configuration Register\n+ */\n+#define DSI_GHCR\t\t\tMMIO32(DSI_BASE + 0x6CU)\n+#define DSI_GHCR_WCMSB_SHIFT\t\t16\n+#define DSI_GHCR_WCMSB_MASK\t\t0xff\n+#define DSI_GHCR_WCLSB_SHIFT\t\t8\n+#define DSI_GHCR_WCLSB_MASK\t\t0xff\n+#define DSI_GHCR_DATA1_SHIFT\t\t16\t/* data 1 in 'short' mode */\n+#define DSI_GHCR_DATA1_MASK\t\t0xff\n+#define DSI_GHCR_DATA0_SHIFT\t\t8\t/* data 0 in 'short' mode */\n+#define DSI_GHCR_DATA0_MASK\t\t0xff","path":"include/libopencm3/stm32/f4/dsi.h","position":330,"original_position":330,"commit_id":"ec89456267feb3ec564f76154c86614272467626","original_commit_id":"ec89456267feb3ec564f76154c86614272467626","user":{"login":"ChuckM","id":532407,"avatar_url":"https://avatars.githubusercontent.com/u/532407?v=3","gravatar_id":"","url":"https://api.github.com/users/ChuckM","html_url":"https://github.com/ChuckM","followers_url":"https://api.github.com/users/ChuckM/followers","following_url":"https://api.github.com/users/ChuckM/following{/other_user}","gists_url":"https://api.github.com/users/ChuckM/gists{/gist_id}","starred_url":"https://api.github.com/users/ChuckM/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ChuckM/subscriptions","organizations_url":"https://api.github.com/users/ChuckM/orgs","repos_url":"https://api.github.com/users/ChuckM/repos","events_url":"https://api.github.com/users/ChuckM/events{/privacy}","received_events_url":"https://api.github.com/users/ChuckM/received_events","type":"User","site_admin":false},"body":"This register is \"dual use\", when you send a \"short\" generic packet (2 or fewer parameters), you include DATA0 and DATA1 in this register, when you send a \"long\" generic packet (3 or more parameters) then you write the length of the packet in here, and push the parameters into GPDR.","created_at":"2016-08-15T22:01:26Z","updated_at":"2016-08-15T22:01:26Z","html_url":"https://github.com/libopencm3/libopencm3/pull/680#discussion_r74843632","pull_request_url":"https://api.github.com/repos/libopencm3/libopencm3/pulls/680","_links":{"self":{"href":"https://api.github.com/repos/libopencm3/libopencm3/pulls/comments/74843632"},"html":{"href":"https://github.com/libopencm3/libopencm3/pull/680#discussion_r74843632"},"pull_request":{"href":"https://api.github.com/repos/libopencm3/libopencm3/pulls/680"}}},"pull_request":{"url":"https://api.github.com/repos/libopencm3/libopencm3/pulls/680","id":80317907,"html_url":"https://github.com/libopencm3/libopencm3/pull/680","diff_url":"https://github.com/libopencm3/libopencm3/pull/680.diff","patch_url":"https://github.com/libopencm3/libopencm3/pull/680.patch","issue_url":"https://api.github.com/repos/libopencm3/libopencm3/issues/680","number":680,"state":"open","locked":false,"title":"stm32/f4: dsi: DSI Peripheral include file","user":{"login":"ChuckM","id":532407,"avatar_url":"https://avatars.githubusercontent.com/u/532407?v=3","gravatar_id":"","url":"https://api.github.com/users/ChuckM","html_url":"https://github.com/ChuckM","followers_url":"https://api.github.com/users/ChuckM/followers","following_url":"https://api.github.com/users/ChuckM/following{/other_user}","gists_url":"https://api.github.com/users/ChuckM/gists{/gist_id}","starred_url":"https://api.github.com/users/ChuckM/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/ChuckM/subscriptions","organizations_url":"https://api.github.com/users/ChuckM/orgs","repos_url":"https://api.github.com/users/ChuckM/repos","events_url":"https://api.github.com/users/ChuckM/events{/privacy}","received_events_url":"https://api.github.com/users/ChuckM/received_events","type":"User","site_admin":false},"body":"Adds the dsi.h file to the f4 path of the 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