{"action":"created","issue":{"url":"https://api.github.com/repos/nocrew/ostis/issues/143","repository_url":"https://api.github.com/repos/nocrew/ostis","labels_url":"https://api.github.com/repos/nocrew/ostis/issues/143/labels{/name}","comments_url":"https://api.github.com/repos/nocrew/ostis/issues/143/comments","events_url":"https://api.github.com/repos/nocrew/ostis/issues/143/events","html_url":"https://github.com/nocrew/ostis/issues/143","id":150415027,"number":143,"title":"Proposal for a generic state machine","user":{"login":"stefanberndtsson","id":692265,"avatar_url":"https://avatars.githubusercontent.com/u/692265?v=3","gravatar_id":"","url":"https://api.github.com/users/stefanberndtsson","html_url":"https://github.com/stefanberndtsson","followers_url":"https://api.github.com/users/stefanberndtsson/followers","following_url":"https://api.github.com/users/stefanberndtsson/following{/other_user}","gists_url":"https://api.github.com/users/stefanberndtsson/gists{/gist_id}","starred_url":"https://api.github.com/users/stefanberndtsson/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/stefanberndtsson/subscriptions","organizations_url":"https://api.github.com/users/stefanberndtsson/orgs","repos_url":"https://api.github.com/users/stefanberndtsson/repos","events_url":"https://api.github.com/users/stefanberndtsson/events{/privacy}","received_events_url":"https://api.github.com/users/stefanberndtsson/received_events","type":"User","site_admin":false},"labels":[{"url":"https://api.github.com/repos/nocrew/ostis/labels/enhancement","name":"enhancement","color":"84b6eb"}],"state":"open","locked":false,"assignee":{"login":"larsbrinkhoff","id":775050,"avatar_url":"https://avatars.githubusercontent.com/u/775050?v=3","gravatar_id":"","url":"https://api.github.com/users/larsbrinkhoff","html_url":"https://github.com/larsbrinkhoff","followers_url":"https://api.github.com/users/larsbrinkhoff/followers","following_url":"https://api.github.com/users/larsbrinkhoff/following{/other_user}","gists_url":"https://api.github.com/users/larsbrinkhoff/gists{/gist_id}","starred_url":"https://api.github.com/users/larsbrinkhoff/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/larsbrinkhoff/subscriptions","organizations_url":"https://api.github.com/users/larsbrinkhoff/orgs","repos_url":"https://api.github.com/users/larsbrinkhoff/repos","events_url":"https://api.github.com/users/larsbrinkhoff/events{/privacy}","received_events_url":"https://api.github.com/users/larsbrinkhoff/received_events","type":"User","site_admin":false},"milestone":null,"comments":6,"created_at":"2016-04-22T16:29:20Z","updated_at":"2016-04-22T18:23:31Z","closed_at":null,"body":"I propose that `ucode` takes on the job of running everything around the instructions, and exceptions.\r\nThe state machine has one state chain for each instruction being executed. A state chain is a sequence\r\nof microcode instructions (`uop`) being executed one after the other. Each `uop` taking 2 8MHz cycles,\r\nand being run on even 8MHz cycles.\r\n\r\nEA is just one or more sections of such a chain, and so are exceptions.\r\n\r\nAll of this assumes the full prefetch with IRC/IR/IRD is in place.\r\n\r\n\r\nSo the main role for an instruction is to setup the chain based on the instruction opcode (steps below may be optional):\r\n\r\n1. Insert any `uop`:s that's needed before any EA\r\n2. Append any EA chain that's relevant for reading\r\n3. The instructions actual operation (ADD, SUB, Shift, a.s.o.)\r\n4. Any EA chain for writing back to memory or such\r\n5. Parts for setting flags\r\n6. Remaining bits and prefetches before the instruction ends\r\n\r\nThe instruction is now only called to setup, after that, `ucode` takes over and steps through the chain.\r\nIf anything would happen that would change the normal execution, like for example a bus error occurs within\r\nthe EA steps, a bus error chain replaces the rest of the instruction chain, and ucode keeps on executing\r\njust like before.\r\n\r\nFor `TRAP` this would essentially be the same thing, except the instruction would just insert the exception\r\nchain for the `TRAP` exception into the chain straight away.\r\n\r\nOther exceptions could be caught when `ucode` parses the end step, and if there is an exception/interrupt\r\npending, append the exception chain, and keep on running a bit longer.\r\n\r\nEvery `uop` is a callback into a function dealing with it. For steps 2 and 4 above, those are callbacks pretty\r\nmuch the way they are in the EA code now. For 1, 3, 5 and 6, they would be provided by the instruction code.\r\n"},"comment":{"url":"https://api.github.com/repos/nocrew/ostis/issues/comments/213540826","html_url":"https://github.com/nocrew/ostis/issues/143#issuecomment-213540826","issue_url":"https://api.github.com/repos/nocrew/ostis/issues/143","id":213540826,"user":{"login":"stefanberndtsson","id":692265,"avatar_url":"https://avatars.githubusercontent.com/u/692265?v=3","gravatar_id":"","url":"https://api.github.com/users/stefanberndtsson","html_url":"https://github.com/stefanberndtsson","followers_url":"https://api.github.com/users/stefanberndtsson/followers","following_url":"https://api.github.com/users/stefanberndtsson/following{/other_user}","gists_url":"https://api.github.com/users/stefanberndtsson/gists{/gist_id}","starred_url":"https://api.github.com/users/stefanberndtsson/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/stefanberndtsson/subscriptions","organizations_url":"https://api.github.com/users/stefanberndtsson/orgs","repos_url":"https://api.github.com/users/stefanberndtsson/repos","events_url":"https://api.github.com/users/stefanberndtsson/events{/privacy}","received_events_url":"https://api.github.com/users/stefanberndtsson/received_events","type":"User","site_admin":false},"created_at":"2016-04-22T18:23:31Z","updated_at":"2016-04-22T18:23:31Z","body":"I think I'd rather see something like separate sequences.\r\n\r\n```\r\nstatic struct u_sequence add_sequence_reg_to_mem[] = {\r\n  add_start,  // Initialisation\r\n  read_register, // Read register operand\r\n  add_compute, // Do addition\r\n  ea_begin_modify, // Write memory operand\r\n  add_finish // Clean up\r\n};\r\n\r\nstatic struct u_sequence add_sequence_mem_to_reg[] = {\r\n  add_start,  // Initialisation\r\n  ea_begin_read, // Read operand\r\n  add_compute, // Do addition\r\n  write_register, // Write register operand\r\n  add_finish // Clean up\r\n};\r\n\r\n\r\nvoid add(struct cpu *cpu, WORD op)\r\n{\r\n  if(op == REG_TO_MEM) {\r\n   u_start_sequence(&add_sequence_reg_to_mem);\r\n  } else {\r\n   u_start_sequence(&add_sequence_mem_to_reg);\r\n  }\r\n}\r\n```"}}