{"push_id":1216849609,"size":10,"distinct_size":10,"ref":"refs/heads/cm-12.1","head":"3f2b00427fbc6b923520810619bb64fd85fc2632","before":"f17569524b7350a0bf2befb21b2f20082bf28e81","commits":[{"sha":"8b996cfad82b2f86e2c80810b0174c568334829f","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":"Trying to enable 2.1GHz overclock again","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/8b996cfad82b2f86e2c80810b0174c568334829f"},{"sha":"0eef3ceecccb6c9fd93f4200ddecf44933ea0c87","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":"Temorarly disable intelliplug and fastcharging +\n ARM: kernel: smp_setup_processor_id() updates\n\nThis patch applies some basic changes to the smp_setup_processor_id()\nARM implementation to make the code that builds cpu_logical_map more\nuniform across the kernel.\n\nThe function now prints the full extent of the boot CPU MPIDR[23:0] and\ninitializes the cpu_logical_map for CPUs up to nr_cpu_ids.\n\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/0eef3ceecccb6c9fd93f4200ddecf44933ea0c87"},{"sha":"acc6e90402f02358a76605547f0d7e65e1171a1c","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":" ARM: 7759/1: decouple CPU offlining from reboot/shutdown\n\nAdd comments to machine_shutdown()/halt()/power_off()/restart() that\ndescribe their purpose and/or requirements re: CPUs being active/not.\n\nIn machine_shutdown(), replace the call to smp_send_stop() with a call\nto\ndisable_nonboot_cpus(). This completely disables all but one CPU, thus\nsatisfying the requirement that only a single CPU be active for kexec.\nAdjust Kconfig dependencies for this change.\n\nIn machine_halt()/power_off()/restart(), call smp_send_stop() directly,\nrather than via machine_shutdown(); these functions don't need to\ncompletely de-activate all CPUs using hotplug, but rather just quiesce\nthem.\n\nRemove smp_kill_cpus(), and its call from smp_send_stop().\nsmp_kill_cpus() was indirectly calling smp_ops.cpu_kill() without\ncalling\nsmp_ops.cpu_die() on the target CPUs first. At least some\nimplementations\nof smp_ops had issues with this; it caused cpu_kill() to hang on Tegra,\nfor example. Since smp_send_stop() is only used for shutdown, halt, and\npower-off, there is no need to attempt any kind of CPU hotplug here.\n\nAdjust Kconfig to reflect that machine_shutdown() (and hence kexec)\nrelies upon disable_nonboot_cpus(). However, this alone doesn't\nguarantee\nthat hotplug will work, or even that hotplug is implemented for a\nparticular piece of HW that a multi-platform zImage runs on. Hence, add\nerror-checking to machine_kexec() to determine whether it did work.\n\nSuggested-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Stephen Warren <swarren@nvidia.com>\nAcked-by: Will Deacon <will.deacon@arm.com>\nTested-by:  Zhangfei Gao <zhangfei.gao@gmail.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>\n\n    master\n\ncommit b90679763ef06cb41dbeab24b07bc1a1c8dd88c3 1 parent 2f68316\ngoogyanas googyanas authored on 6 Oct 2014\nShowing\nwith 45 additions and 19 deletions.\n6  arch/arm/kernel/machine_kexec.c\n@@ -110,7 +110,11 @@ void machine_kexec(struct kimage *image)\nunsigned long reboot_code_buffer_phys;\nvoid *reboot_code_buffer;\n-\n+ if (num_online_cpus() > 1) {\n+ pr_err(\"kexec: error: multiple CPUs still online\\n\");\n+ return;\n+ }\n+\npage_list = image->head & PAGE_MASK;\n/* we need both effective and real address here */\n45  arch/arm/kernel/process.c\n@@ -277,29 +277,38 @@\nlocal_irq_enable();\n}\nrcu_idle_exit();\ntick_nohz_idle_exit();\nidle_notifier_call_chain(IDLE_END);\nschedule_preempt_disabled();\nif (cpu_is_offline(smp_processor_id()))\ncpu_die();\n}\n}\nstatic char reboot_mode = 'h';\nint __init reboot_setup(char *str)\n{\nreboot_mode = str[0];\nreturn 1;\n}\n__setup(\"reboot=\", reboot_setup);\n+/*\n+ * Called by kexec, immediately prior to machine_kexec().\n+ *\n+ * This must completely disable all secondary CPUs; simply causing those CPUs\n+ * to execute e.g. a RAM-based pin loop is not sufficient. This allows the\n+ * kexec'd kernel to use any and all RAM as it sees fit, without having to\n+ * avoid any code or data used by any SW CPU pin loop. The CPU hotplug\n+ * functionality embodied in disable_nonboot_cpus() to achieve this.\n+ */\n+\nvoid machine_shutdown(void)\n{\n- preempt_disable();\n/*\n* Disable preemption so we're guaranteed to\n* run to power off or reboot and prevent\n* the possibility of switching to another\n* thread that might wind up blocking on\n* one of the stopped CPUs.\n*/\npreempt_disable();\n- smp_send_stop();\n+ disable_nonboot_cpus();\n}\n+/*\n+ * Halting simply requires that the secondary CPUs stop performing any\n+ * activity (executing tasks, handling interrupts). smp_send_stop()\n+ * achieves this.\n+ */\n+\nvoid machine_halt(void)\n{\n- machine_shutdown();\n+ preempt_disable();\n+ smp_send_stop();\nlocal_irq_disable();\nwhile (1);\n}\n+/*\n+ * Power-off simply requires that the secondary CPUs stop performing any\n+ * activity (executing tasks, handling interrupts). smp_send_stop()\n+ * achieves this. When the system power is turned off, it will take all CPUs\n+ * with it.\n+ */\n+\nvoid machine_power_off(void)\n{\n- machine_shutdown();\n+ smp_send_stop();\nif (pm_power_off)\npm_power_off();\n}\n+/*\n+ * Restart requires that the secondary CPUs stop performing any activity\n+ * while the primary CPU resets the system. Systems with a single CPU can\n+ * use soft_restart() as their machine descriptor's .restart hook, since that\n+ * will cause the only available CPU to reset. Systems with multiple CPUs must\n+ * provide a HW restart implementation, to ensure that all CPUs reset at once.\n+ * This is required so that any code running after reset on the primary CPU\n+ * doesn't have to co-ordinate with other CPUs to ensure they aren't still\n+ * executing pre-reset code, and using RAM that the primary CPU's code wishes\n+ * to use. Implementing such co-ordination would be essentially impossible.\n+ */\n+\nvoid machine_restart(char *cmd)\n{\n- machine_shutdown();\n+ smp_send_stop();\n/* Flush the console to make sure all the relevant messages make it\n* out to the console drivers */\n13  arch/arm/kernel/smp.c\n@@ -683,17 +683,6 @@ void smp_send_reschedule(int cpu)\nsmp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);\n}\n-#ifdef CONFIG_HOTPLUG_CPU\n-static void smp_kill_cpus(cpumask_t *mask)\n-{\n- unsigned int cpu;\n- for_each_cpu(cpu, mask)\n- platform_cpu_kill(cpu);\n-}\n-#else\n-static void smp_kill_cpus(cpumask_t *mask) { }\n-#endif\n-\nvoid smp_send_stop(void)\n{\nunsigned long timeout;\n@@ -711,8 +700,6 @@ void smp_send_stop(void)\nif (num_active_cpus() > 1)\npr_warning(\"SMP: failed to stop secondary CPUs\\n\");\n-\n- smp_kill_cpus(&mask);\n}\n/*\nLuca Grifo\n\n    Write\n    Preview\n\nMarkdown supported\nEdit in fullscreen\n\nAttach images by dragging & dropping or selecting them.","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/acc6e90402f02358a76605547f0d7e65e1171a1c"},{"sha":"2a14c72708c6fe0e4e3dc125e7be036dfb96950b","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":" ARM: 7587/1: implement optimized percpu variable access. Changed some 2.1GHz values and disabled intelliplug\n\nUse the previously unused TPIDRPRW register to store percpu offsets.\nTPIDRPRW is only accessible in PL1, so it can only be used in the\nkernel.\n\nThis replaces 2 loads with a mrc instruction for each percpu variable\naccess. With hackbench, the performance improvement is 1.4% on Cortex-A9\n(highbank). Taking an average of 30 runs of \"hackbench -l 1000\" yields:\n\nBefore: 6.2191\nAfter: 6.1348\n\nWill Deacon reported similar delta on v6 with 11MPCore.\n\nThe asm \"memory clobber\" are needed here to ensure the percpu offset\ngets reloaded. Testing by Will found that this would not happen in\n__schedule() which is a bit of a special case as preemption is disabled\nbut the execution can move cores.\n\nSigned-off-by: Rob Herring <rob.herring@calxeda.com>\nAcked-by: Will Deacon <will.deacon@arm.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>\n\nConflicts:\n\tarch/arm/kernel/smp.c","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/2a14c72708c6fe0e4e3dc125e7be036dfb96950b"},{"sha":"9dcef4e157239fe11d95dd02a57fc0210b9c3e5a","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":" ARM: kernel: smp_setup_processor_id() updates and added missing Percpu file\n\nThis patch applies some basic changes to the smp_setup_processor_id()\nARM implementation to make the code that builds cpu_logical_map more\nuniform across the kernel.\n\nThe function now prints the full extent of the boot CPU MPIDR[23:0] and\ninitializes the cpu_logical_map for CPUs up to nr_cpu_ids.\n\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/9dcef4e157239fe11d95dd02a57fc0210b9c3e5a"},{"sha":"51b6af5433ad7dc729d3ee8e800fcf06a1e43a3c","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":" ARM: kernel: smp_setup_processor_id() updates (SORRY)\n\nThis patch applies some basic changes to the smp_setup_processor_id()\nARM implementation to make the code that builds cpu_logical_map more\nuniform across the kernel.\n\nThe function now prints the full extent of the boot CPU MPIDR[23:0] and\ninitializes the cpu_logical_map for CPUs up to nr_cpu_ids.\n\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/51b6af5433ad7dc729d3ee8e800fcf06a1e43a3c"},{"sha":"87d2d2a4c8480dbc399ad8f87b14cfafccf2492c","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":" ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register\n\nThe ISAR0 register indicates support for the SDIV and UDIV\ninstructions in both the Thumb and ARM instruction set. Read the\nregister to detect the supported instructions and update the\nelf_hwcap mask as appropriate. This is better than adding more\nand more cpuid checks in proc-v7.S for each new cpu variant that\nsupports these instructions.\n\nAcked-by: Will Deacon <will.deacon@arm.com>\nCc: Stepan Moskovchenko <stepanm@codeaurora.org>\nSigned-off-by: Stephen Boyd <sboyd@codeaurora.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/87d2d2a4c8480dbc399ad8f87b14cfafccf2492c"},{"sha":"53ea9ea95cc1f907bcd74a7a2a9797d80f0c1a79","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":" ARM: kernel: build MPIDR hash function data structure\n\nOn ARM SMP systems, cores are identified by their MPIDR register.\nThe MPIDR guidelines in the ARM ARM do not provide strict enforcement of\nMPIDR layout, only recommendations that, if followed, split the MPIDR\non ARM 32 bit platforms in three affinity levels. In multi-cluster\nsystems like big.LITTLE, if the affinity guidelines are followed, the\nMPIDR can not be considered an index anymore. This means that the\nassociation between logical CPU in the kernel and the HW CPU identifier\nbecomes somewhat more complicated requiring methods like hashing to\nassociate a given MPIDR to a CPU logical index, in order for the look-up\nto be carried out in an efficient and scalable way.\n\nThis patch provides a function in the kernel that starting from the\ncpu_logical_map, implement collision-free hashing of MPIDR values by\nchecking\nall significative bits of MPIDR affinity level bitfields. The hashing\ncan then be carried out through bits shifting and ORing; the resulting\nhash algorithm is a collision-free though not minimal hash that can be\nexecuted with few assembly instructions. The mpidr is filtered through a\nmpidr mask that is built by checking all bits that toggle in the set of\nMPIDRs corresponding to possible CPUs. Bits that do not toggle do not\ncarry\ninformation so they do not contribute to the resulting hash.\n\nPseudo code:\n\n/* check all bits that toggle, so they are required */\nfor (i = 1, mpidr_mask = 0; i < num_possible_cpus(); i++)\n\tmpidr_mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));\n\n/*\n* Build shifts to be applied to aff0, aff1, aff2 values to hash the\nmpidr\n* fls() returns the last bit set in a word, 0 if none\n* ffs() returns the first bit set in a word, 0 if none\n*/\nfs0 = mpidr_mask[7:0] ? ffs(mpidr_mask[7:0]) - 1 : 0;\nfs1 = mpidr_mask[15:8] ? ffs(mpidr_mask[15:8]) - 1 : 0;\nfs2 = mpidr_mask[23:16] ? ffs(mpidr_mask[23:16]) - 1 : 0;\nls0 = fls(mpidr_mask[7:0]);\nls1 = fls(mpidr_mask[15:8]);\nls2 = fls(mpidr_mask[23:16]);\nbits0 = ls0 - fs0;\nbits1 = ls1 - fs1;\nbits2 = ls2 - fs2;\naff0_shift = fs0;\naff1_shift = 8 + fs1 - bits0;\naff2_shift = 16 + fs2 - (bits0 + bits1);\nu32 hash(u32 mpidr) {\n\tu32 l0, l1, l2;\n\tu32 mpidr_masked = mpidr & mpidr_mask;\n\tl0 = mpidr_masked & 0xff;\n\tl1 = mpidr_masked & 0xff00;\n\tl2 = mpidr_masked & 0xff0000;\n\treturn (l0 >> aff0_shift | l1 >> aff1_shift | l2 >> aff2_shift);\n}\n\nThe hashing algorithm relies on the inherent properties set in the ARM\nARM\nrecommendations for the MPIDR. Exotic configurations, where for instance\nthe\nMPIDR values at a given affinity level have large holes, can end up\nrequiring\nbig hash tables since the compression of values that can be achieved\nthrough\nshifting is somewhat crippled when holes are present. Kernel warns if\nthe number of buckets of the resulting hash table exceeds the number of\npossible CPUs by a factor of 4, which is a symptom of a very sparse HW\nMPIDR configuration.\n\nThe hash algorithm is quite simple and can easily be implemented in\nassembly\ncode, to be used in code paths where the kernel virtual address space is\nnot set-up (ie cpu_resume) and instruction and data fetches are strongly\nordered so code must be compact and must carry out few data accesses.\n\nCc: Will Deacon <will.deacon@arm.com>\nCc: Catalin Marinas <catalin.marinas@arm.com>\nCc: Russell King <linux@arm.linux.org.uk>\nCc: Colin Cross <ccross@android.com>\nCc: Santosh Shilimkar <santosh.shilimkar@ti.com>\nCc: Daniel Lezcano <daniel.lezcano@linaro.org>\nCc: Amit Kucheria <amit.kucheria@linaro.org>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>\nReviewed-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Nicolas Pitre <nico@linaro.org>\nTested-by: Shawn Guo <shawn.guo@linaro.org>\nTested-by: Kevin Hilman <khilman@linaro.org>\nTested-by: Stephen Warren <swarren@wwwdotorg.org>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/53ea9ea95cc1f907bcd74a7a2a9797d80f0c1a79"},{"sha":"54a110cfd81ed6bb329f0239a880fbb65355b9ef","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":" ARM: cacheflush: add synchronization helpers for mixed cache state ac…\n\n…cesses\n\nAlgorithms used by the MCPM layer rely on state variables which are\naccessed while the cache is either active or inactive, depending\non the code path and the active state.\n\nThis patch introduces generic cache maintenance helpers to provide the\nnecessary cache synchronization for such state variables to always hit\nmain memory in an ordered way.\n\nSigned-off-by: Nicolas Pitre <nico@linaro.org>\nAcked-by: Russell King <rmk+kernel@arm.linux.org.uk>\nAcked-by: Dave Martin <dave.martin@linaro.org>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/54a110cfd81ed6bb329f0239a880fbb65355b9ef"},{"sha":"3f2b00427fbc6b923520810619bb64fd85fc2632","author":{"name":"Tkkg1994","email":"36a572fc51e66d8112975700b5c9381902a9b016@outlook.com"},"message":"Add missing fastcharge.h file","distinct":true,"url":"https://api.github.com/repos/crimsonthunder/android_kernel_samsung_chagalllte/commits/3f2b00427fbc6b923520810619bb64fd85fc2632"}]}
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