{"push_id":1241181102,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"0f73cca02b645267cb11ab8ddf1ba88af5ec3246","before":"9e730bd16418d76e400f87cf852b53f960d1d5b3","commits":[{"sha":"3cdbd7528bd46584551de60f3c47e63963dda117","author":{"name":"Ard Biesheuvel","email":"80b89d4a5c0c8f00cebbb9c7d8a672c776f22af1@linaro.org"},"message":"BaseTools CLANG35: add missing XIP flags for AARCH64\n\nWhen building for AARCH64, code that may execute with the MMU off should\nnot perform unaligned accesses, which is why we set -mstrict-align for\nBASE, SEC, PEI_CORE and PEIM modules when building with GCCx. However,\nthis setting is missing from CLANG35 so set it there as well.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nReviewed-by: Liming Gao <liming.gao@intel.com>","distinct":true,"url":"https://api.github.com/repos/tianocore/edk2/commits/3cdbd7528bd46584551de60f3c47e63963dda117"},{"sha":"0f73cca02b645267cb11ab8ddf1ba88af5ec3246","author":{"name":"Ard Biesheuvel","email":"80b89d4a5c0c8f00cebbb9c7d8a672c776f22af1@linaro.org"},"message":"BaseTools ARM: impose strict alignment only for XIP modules\n\nGiven that we only support ARMv7 and up in Tianocore (due to the fact\nthat the PI spec mandates that the PEI services table pointer be stored\nin the TPIDRURW register, which is not available on earlier CPUs), we can\nassume that any code executing with the MMU on may perform unaligned\naccesses (since the AArch32 bindings in the UEFI spec stipulate that\nunaligned accesses should be allowed if supported by the CPU)\n\nSo relax the alignment restrictions to XIP modules only, i.e., BASE, SEC,\nPEI_CORE and PEIM type modules, exactly like we do for AARCH64 already.\n\nContributed-under: TianoCore Contribution Agreement 1.0\nSigned-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nReviewed-by: Liming Gao <liming.gao@intel.com>","distinct":true,"url":"https://api.github.com/repos/tianocore/edk2/commits/0f73cca02b645267cb11ab8ddf1ba88af5ec3246"}]}
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