{"push_id":1136727342,"size":3,"distinct_size":3,"ref":"refs/heads/linux2","head":"b37d1da8f09996c901a5b46ee376bd576fe9595a","before":"bf6d13c4bd76a7579d19c39c2f0c96c0057b6f54","commits":[{"sha":"3b3b303f6e6838290ef431b807bec86c07b6bdb3","author":{"name":"Patrick Tjin","email":"46d88a89e92edd8988129e9c71eaf27efb6541ae@google.com"},"message":"ARM: gic: remove redundant debug message\n\nRemove log message which was made redundant.\n\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/android_kernel_sony_msm8974/commits/3b3b303f6e6838290ef431b807bec86c07b6bdb3"},{"sha":"83f96d6ac79656aa8cf00e454c0c655a89925a24","author":{"name":"Nicolas Pitre","email":"821418b0a29e813296bdaa58f6aecc4445fd1b69@linaro.org"},"message":"ARM: gic: use a private mapping for CPU target interfaces\n\nThe GIC interface numbering does not necessarily follow the logical\nCPU numbering, especially for complex topologies such as multi-cluster\nsystems.\n\nFortunately we can easily probe the GIC to create a mapping as the\nInterrupt Processor Targets Registers for the first 32 interrupts are\nread-only, and each field returns a value that always corresponds to\nthe processor reading the register.\n\nInitially all mappings target all CPUs in case an IPI is required to\nboot secondary CPUs.  It is refined as those CPUs discover what their\nactual mapping is.\n\nSigned-off-by: Nicolas Pitre <nico@linaro.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/android_kernel_sony_msm8974/commits/83f96d6ac79656aa8cf00e454c0c655a89925a24"},{"sha":"b37d1da8f09996c901a5b46ee376bd576fe9595a","author":{"name":"Pranav Vashi","email":"03be7ddd3681236397de02d2b35bff2ebe2e3300@gmail.com"},"message":"ARM: gic: Bring inline with upstream\n\nARM: gic: fix restore order of distributor registers in gic_cpu_restore()\n\nSimilar to gic_dist_restore(), the GIC config, priority and enable\nregisters should be restored in that order. Fix this in gic_cpu_restore()\nwhich currently restores the enable registers before the configuration\nregisters.\n\nSigned-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>\n\nARM: GIC: fix GIC cpumask initialization\n\nPunit Agrawal reports:\n> I was trying to boot 3.8-rc5 on Realview EB 11MPCore using\n> realview-smp_defconfig as a starting point but the kernel failed to\n> progress past the log below (config attached).\n>\n> Pawel suggested I try reverting 384a290283f - \"ARM: gic: use a private\n> mapping for CPU target interfaces\" that you've authored. With this\n> commit reverted the kernel boots.\n>\n> I am not quite sure why the commit breaks 11MPCore but Pawel (cc'd)\n> might be able to shed light on that.\n\nSome early GIC implementations return zero for the first distributor\nCPU routing register.  This means we can't rely on that telling us\nwhich CPU interface we're connected to.  We know that these platforms\nimplement PPIs for IRQs 29-31 - but we shouldn't assume that these\nwill always be populated.\n\nSo, instead, scan for a non-zero CPU routing register in the first\n32 IRQs and use that as our CPU mask.\n\nChange-Id: I264edd7273353e300d7d1ef096709f9d87b9ec78\nReported-by: Punit Agrawal <punit.agrawal@arm.com>\nReviewed-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nirqchip: gic: Perform the gic_secondary_init() call via CPU notifier\n\nAll the calls to gic_secondary_init() pass 0 as the first argument.\nSince this function is called on each CPU when starting, it can be done\nin a platform-independent way via a CPU notifier registered by the GIC\ncode.\n\nChange-Id: I729e09097230eb2f93fb730f1d58a279c5ef51f8\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nAcked-by: Stephen Warren <swarren@nvidia.com>\nAcked-by: Viresh Kumar <viresh.kumar@linaro.org>\nAcked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>\nAcked-by: Rob Herring <rob.herring@calxeda.com>\nAcked-by: Simon Horman <horms+renesas@verge.net.au>\nTested-by: Simon Horman <horms+renesas@verge.net.au>\nAcked-by: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>\nTested-by: Dinh Nguyen <dinguyen@altera.com>\nAcked-by: Nicolas Pitre <nico@linaro.org>\nTested-by: Marc Zyngier <marc.zyngier@arm.com>\nCc: Russell King <linux@arm.linux.org.uk>\nCc: Thomas Gleixner <tglx@linutronix.de>\nCc: Kukjin Kim <kgene.kim@samsung.com>\nCc: Sascha Hauer <kernel@pengutronix.de>\nCc: David Brown <davidb@codeaurora.org>\nCc: Bryan Huntsman <bryanh@codeaurora.org>\nCc: Tony Lindgren <tony@atomide.com>\nCc: Magnus Damm <magnus.damm@gmail.com>\nCc: Shiraz Hashim <shiraz.hashim@st.com>\nCc: Linus Walleij <linus.walleij@linaro.org>\nCc: Will Deacon <will.deacon@arm.com>\nCc: Kukjin Kim <kgene.kim@samsung.com>\nCc: Barry Song <baohua.song@csr.com>\nSigned-off-by: Pranav Vashi <neobuddy89@gmail.com>","distinct":true,"url":"https://api.github.com/repos/tunturn/android_kernel_sony_msm8974/commits/b37d1da8f09996c901a5b46ee376bd576fe9595a"}]}
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