{"push_id":1425669218,"size":5,"distinct_size":5,"ref":"refs/heads/marvell/armada-3700-spi-mainline-v2","head":"0821ef2c93fd806e37013061946446466e10a86e","before":"8a5e97fbc6791883e77f5d13ab63f57dda3136c2","commits":[{"sha":"b0d0504b3571a18d7603744cb45e172f09ed76c9","author":{"name":"Romain Perier","email":"052754d2a1b17922abb8910db2b5184d924f0c9e@free-electrons.com"},"message":"spi: Add basic support for Armada 3700 SPI Controller\n\nMarvell Armada 3700 SoC comprises an SPI Controller. This Controller\nsupports up to 4 SPI slave devices, with dedicated chip selects, supports\nSPI mode 0/1/2 and 3, CPIO or Fifo mode with DMA transfers and different\nSPI transfer mode (Single, Dual or Quad).\n\nThis commit adds basic driver support for CPIO mode and single SPI\ntransfer. In this mode, the CPU asserts cs, outputs or inputs data from\nthe current SPI device. Data transfers are copied by 1 or 4 bytes using\nthe SPI registers.\n\nSigned-off-by: Romain Perier <romain.perier@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/rperier/linux/commits/b0d0504b3571a18d7603744cb45e172f09ed76c9"},{"sha":"72c6cf3133292ecfaf9823f16e23a2c5c28d83f7","author":{"name":"Romain Perier","email":"052754d2a1b17922abb8910db2b5184d924f0c9e@free-electrons.com"},"message":"spi: armada-3700: Add support for the FIFO mode\n\nIn FIFO mode, dedicated registers are used to store the instruction,\nthe address, the read mode and the data. Write and Read FIFO are used\nto store the outcoming or incoming data. The CPU no longer has to assert\neach byte. The data FIFOs are accessible via DMA or by the CPU.\n\nThis commit adds support for the FIFO mode with the CPU.\n\nSigned-off-by: Romain Perier <romain.perier@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/rperier/linux/commits/72c6cf3133292ecfaf9823f16e23a2c5c28d83f7"},{"sha":"2dccaa141bfc7e38d24c6ea1957135016e0db1b6","author":{"name":"Romain Perier","email":"052754d2a1b17922abb8910db2b5184d924f0c9e@free-electrons.com"},"message":"dt-bindings: spi: Add documentation for the Armada 3700 SPI Controller\n\nThis adds the devicetree bindings documentation for the SPI controller\npresent in the Marvell Armada 3700 SoCs.\n\nSigned-off-by: Romain Perier <romain.perier@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/rperier/linux/commits/2dccaa141bfc7e38d24c6ea1957135016e0db1b6"},{"sha":"ecaa213648785b75489f040969c949b92325a638","author":{"name":"Romain Perier","email":"052754d2a1b17922abb8910db2b5184d924f0c9e@free-electrons.com"},"message":"arm64: dts: marvell: Add definition of SPI controller for Armada 3700\n\nArmada 3700 SoC has an SPI Controller, this commit adds the definition\nof the SPI device node at the SoC level.\n\nSigned-off-by: Romain Perier <romain.perier@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/rperier/linux/commits/ecaa213648785b75489f040969c949b92325a638"},{"sha":"0821ef2c93fd806e37013061946446466e10a86e","author":{"name":"Romain Perier","email":"052754d2a1b17922abb8910db2b5184d924f0c9e@free-electrons.com"},"message":"arm64: dts: marvell: Enable spi0 on the board Armada-3720-db\n\nThis commit enables the device node spi0 on the official development\nboard for the Marvell Armada 3700. It also adds sub-node for the 128Mb\nSPI-NOR present on the board.\n\nSigned-off-by: Romain Perier <romain.perier@free-electrons.com>","distinct":true,"url":"https://api.github.com/repos/rperier/linux/commits/0821ef2c93fd806e37013061946446466e10a86e"}]}
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