{"action":"opened","issue":{"url":"https://api.github.com/repos/ucb-bar/firrtl/issues/131","repository_url":"https://api.github.com/repos/ucb-bar/firrtl","labels_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/131/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/131/comments","events_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/131/events","html_url":"https://github.com/ucb-bar/firrtl/issues/131","id":149566095,"number":131,"title":"Chirrtl port clocks get used before their declaration","user":{"login":"jackkoenig","id":8584418,"avatar_url":"https://avatars.githubusercontent.com/u/8584418?v=3","gravatar_id":"","url":"https://api.github.com/users/jackkoenig","html_url":"https://github.com/jackkoenig","followers_url":"https://api.github.com/users/jackkoenig/followers","following_url":"https://api.github.com/users/jackkoenig/following{/other_user}","gists_url":"https://api.github.com/users/jackkoenig/gists{/gist_id}","starred_url":"https://api.github.com/users/jackkoenig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jackkoenig/subscriptions","organizations_url":"https://api.github.com/users/jackkoenig/orgs","repos_url":"https://api.github.com/users/jackkoenig/repos","events_url":"https://api.github.com/users/jackkoenig/events{/privacy}","received_events_url":"https://api.github.com/users/jackkoenig/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2016-04-19T19:54:43Z","updated_at":"2016-04-19T19:54:43Z","closed_at":null,"body":"The following Chirrtl overwrites the clock for a port:\r\n```\r\ncircuit Bug :\r\n  module Bug :\r\n    input clk : Clock\r\n    smem ram : UInt<32>[128]\r\n\r\n    node newClock = clk\r\n    infer mport y = ram[UInt(2)], newClock\r\n    y <= UInt(3)\r\n```\r\nRunning the passes to remove Chirrtl results in:\r\n```\r\ncircuit Bug :                                                                                                                                                                                                                                                                \r\n  module Bug : \r\n    input clk : Clock\r\n    mem ram : \r\n      data-type => UInt<32>\r\n      depth => 128\r\n      read-latency => 1\r\n      write-latency => 1\r\n      writer => y\r\n      read-under-write => undefined\r\n    ram.y.addr is invalid\r\n    ram.y.clk <= newClock\r\n    ram.y.en <= UInt<1>(\"h0\")\r\n    ram.y.data is invalid\r\n    ram.y.mask <= UInt<1>(\"h0\")\r\n    node newClock = clk\r\n    ram.y.addr <= UInt<2>(\"h2\")\r\n    ram.y.en <= UInt<1>(\"h1\")\r\n    ram.y.data <= UInt<2>(\"h3\")\r\n    ram.y.mask <= UInt<1>(\"h1\")\r\n```\r\nnewClock is being used before it is declared"}}