{"push_id":1436456844,"size":108,"distinct_size":67,"ref":"refs/heads/tgt-hppa","head":"a2663859b0100799c8d93831a3bb2fbaae4206d7","before":"95498915a22bea0cd60a97767012201f9b711e62","commits":[{"sha":"804ba7c10bbc66bb8a8aa73ecc60f620da7423d5","author":{"name":"Anthony PERARD","email":"fe5c17da6e226e2dea68fcc2f543ea615504bdf2@citrix.com"},"message":"xen: Fix xenpv machine initialisation\n\nWhen using QEMU for Xen PV guest, QEMU abort with:\nxen-common.c:118:xen_init: Object 0x7f2b8325dcb0 is not an instance of type generic-pc-machine\n\nThis is because the machine 'xenpv' also use accel=xen. Moving the code\nto xen_hvm_init() fix the issue.\n\nThis fix 021746c131cdfeab9d82ff918795a9f18d20d7ae.\n\nSigned-off-by: Anthony PERARD <anthony.perard@citrix.com>\nSigned-off-by: Stefano Stabellini <sstabellini@kernel.org>\nReviewed-by: Eduardo Habkost <ehabkost@redhat.com>\nReviewed-by: Stefano Stabellini <sstabellini@kernel.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/804ba7c10bbc66bb8a8aa73ecc60f620da7423d5"},{"sha":"bd7fa4ac5f7589deb4dd390146c51e43bd9bb37f","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"docs: new design document multi-thread-tcg.txt\n\nThis documents the current design for upgrading TCG emulation to take\nadvantage of modern CPUs by running a thread-per-CPU. The document goes\nthrough the various areas of the code affected by such a change and\nproposes design requirements for each part of the solution.\n\nThe text marked with (Current solution[s]) to document what the current\napproaches being used are.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\nMessage-Id: <20161109145748.27282-2-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/bd7fa4ac5f7589deb4dd390146c51e43bd9bb37f"},{"sha":"2e72556ab20f545b12ff3c8bd3212d84c293b4c5","author":{"name":"KONRAD Frederic","email":"65d957747955457a3358fd7137262a55c9d81c70@greensocs.com"},"message":"tcg: add options for enabling MTTCG\n\nWe know there will be cases where MTTCG won't work until additional work\nis done in the front/back ends to support. It will however be useful to\nbe able to turn it on.\n\nAs a result MTTCG will default to off unless the combination is\nsupported. However the user can turn it on for the sake of testing.\n\nSigned-off-by: KONRAD Frederic <fred.konrad@greensocs.com>\n[AJB: move to -accel tcg,thread=multi|single, defaults]\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-Id: <20161109145748.27282-3-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/2e72556ab20f545b12ff3c8bd3212d84c293b4c5"},{"sha":"b739941beaa8cf56cc3cf2cffbadf8126e7aee94","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"tcg: add kick timer for single-threaded vCPU emulation\n\nCurrently we rely on the side effect of the main loop grabbing the\niothread_mutex to give any long running basic block chains a kick to\nensure the next vCPU is scheduled. As this code is being re-factored and\nrationalised we now do it explicitly here.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\nMessage-Id: <20161109145748.27282-4-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/b739941beaa8cf56cc3cf2cffbadf8126e7aee94"},{"sha":"2332342e27101dcc9cc361c137aeaaaac87f3ede","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"tcg: rename tcg_current_cpu to tcg_current_rr_cpu\n\n..and make the definition local to cpus. In preparation for MTTCG the\nconcept of a global tcg_current_cpu will no longer make sense. However\nwe still need to keep track of it in the single-threaded case to be able\nto exit quickly when required.\n\nqemu_cpu_kick_no_halt() moves and becomes qemu_cpu_kick_rr_cpu() to\nemphasise its use-case. qemu_cpu_kick now kicks the relevant cpu as\nwell as qemu_kick_rr_cpu() which will become a no-op in MTTCG.\n\nFor the time being the setting of the global exit_request remains.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-Id: <20161109145748.27282-5-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/2332342e27101dcc9cc361c137aeaaaac87f3ede"},{"sha":"2212a93fb9cfe9def640a6bb88ec5d7b01783f0e","author":{"name":"Jan Kiszka","email":"43ec288f57ce2167dc702d43d1d371e3e3fbd31f@siemens.com"},"message":"tcg: drop global lock during TCG code execution\n\nThis finally allows TCG to benefit from the iothread introduction: Drop\nthe global mutex while running pure TCG CPU code. Reacquire the lock\nwhen entering MMIO or PIO emulation, or when leaving the TCG loop.\n\nWe have to revert a few optimization for the current TCG threading\nmodel, namely kicking the TCG thread in qemu_mutex_lock_iothread and not\nkicking it in qemu_cpu_kick. We also need to disable RAM block\nreordering until we have a more efficient locking mechanism at hand.\n\nStill, a Linux x86 UP guest and my Musicpal ARM model boot fine here.\nThese numbers demonstrate where we gain something:\n\n20338 jan       20   0  331m  75m 6904 R   99  0.9   0:50.95 qemu-system-arm\n20337 jan       20   0  331m  75m 6904 S   20  0.9   0:26.50 qemu-system-arm\n\nThe guest CPU was fully loaded, but the iothread could still run mostly\nindependent on a second core. Without the patch we don't get beyond\n\n32206 jan       20   0  330m  73m 7036 R   82  0.9   1:06.00 qemu-system-arm\n32204 jan       20   0  330m  73m 7036 S   21  0.9   0:17.03 qemu-system-arm\n\nWe don't benefit significantly, though, when the guest is not fully\nloading a host CPU.\n\nSigned-off-by: Jan Kiszka <jan.kiszka@siemens.com>\nMessage-Id: <1439220437-23957-10-git-send-email-fred.konrad@greensocs.com>\n[FK: Rebase, fix qemu_devices_reset deadlock, rm address_space_* mutex]\nSigned-off-by: KONRAD Frederic <fred.konrad@greensocs.com>\n[EGC: fixed iothread lock for cpu-exec IRQ handling]\nSigned-off-by: Emilio G. Cota <cota@braap.org>\n[AJB: -smp single-threaded fix, rm old info from commit msg, review updates]\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\nMessage-Id: <20161109145748.27282-6-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/2212a93fb9cfe9def640a6bb88ec5d7b01783f0e"},{"sha":"b4aa63505afd927f2275a6f585feaeff9c7ee996","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"tcg: remove global exit_request\n\nThere are now only two uses of the global exit_request left.\n\nThe first ensures we exit the run_loop when we first start to process\npending work and in the kick handler. This is just as easily done by\nsetting the first_cpu->exit_request flag.\n\nThe second use is in the round robin kick routine. The global\nexit_request ensured every vCPU would set its local exit_request and\ncause a full exit of the loop. Now the iothread isn't being held while\nrunning we can just rely on the kick handler to push us out as intended.\n\nWe lightly re-factor the main vCPU thread to ensure cpu->exit_requests\ncause us to exit the main loop and process any IO requests that might\ncome along.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-Id: <20161109145748.27282-7-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/b4aa63505afd927f2275a6f585feaeff9c7ee996"},{"sha":"06a7f53e4081329b8f66f2fe9c79c186a51af3ad","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"tcg: enable tb_lock() for SoftMMU\n\ntb_lock() has long been used for linux-user mode to protect code\ngeneration. By enabling it now we prepare for MTTCG and ensure all code\ngeneration is serialised by this lock. The other major structure that\nneeds protecting is the l1_map and its PageDesc structures. For the\nSoftMMU case we also use tb_lock() to protect these structures instead\nof linux-user mmap_lock() which as the name suggests serialises updates\nto the structure as a result of guest mmap operations.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nMessage-Id: <20161109145748.27282-8-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/06a7f53e4081329b8f66f2fe9c79c186a51af3ad"},{"sha":"02a0d9511143da14654abdeb64a679a6e8c90317","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"tcg: enable thread-per-vCPU\n\nThere are a couple of changes that occur at the same time here:\n\n  - introduce a single vCPU qemu_tcg_cpu_thread_fn\n\n  One of these is spawned per vCPU with its own Thread and Condition\n  variables. qemu_tcg_rr_cpu_thread_fn is the new name for the old\n  single threaded function.\n\n  - the TLS current_cpu variable is now live for the lifetime of MTTCG\n    vCPU threads. This is for future work where async jobs need to know\n    the vCPU context they are operating in.\n\nThe user to switch on multi-thread behaviour and spawn a thread\nper-vCPU. For a simple test kvm-unit-test like:\n\n  ./arm/run ./arm/locking-test.flat -smp 4 -accel tcg,thread=multi\n\nWill now use 4 vCPU threads and have an expected FAIL (instead of the\nunexpected PASS) as the default mode of the test has no protection when\nincrementing a shared variable.\n\nWe enable the parallel_cpus flag to ensure we generate correct barrier\nand atomic code if supported by the front and backends. As each back end\nand front end is updated they can add CONFIG_MTTCG_TARGET and\nCONFIG_MTTCG_HOST to their respective make configurations so\ndefault_mttcg_enabled does the right thing.\n\nSigned-off-by: KONRAD Frederic <fred.konrad@greensocs.com>\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>\n[AJB: Some fixes, conditionally, commit rewording]\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\nMessage-Id: <20161109145748.27282-9-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/02a0d9511143da14654abdeb64a679a6e8c90317"},{"sha":"a51abcb460d2624db054a850d8292e02ecabf62f","author":{"name":"Pranith Kumar","email":"549aca8acc4e906d9245f0a683b00fa5de6b5955@gmail.com"},"message":"tcg: handle EXCP_ATOMIC exception for system emulation\n\nThe patch enables handling atomic code in the guest. This should be\npreferably done in cpu_handle_exception(), but the current assumptions\nregarding when we can execute atomic sections cause a deadlock.\n\nSigned-off-by: Pranith Kumar <bobby.prani@gmail.com>\n[AJB: tweak title]\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-10-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/a51abcb460d2624db054a850d8292e02ecabf62f"},{"sha":"1b7140aca52c7de22933952c85350a2e319fc99f","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"cputlb: add assert_cpu_is_self checks\n\nFor SoftMMU the TLB flushes are an example of a task that can be\ntriggered on one vCPU by another. To deal with this properly we need to\nuse safe work to ensure these changes are done safely. The new assert\ncan be enabled while debugging to catch these cases.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-11-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/1b7140aca52c7de22933952c85350a2e319fc99f"},{"sha":"9d5afb6dfd54c5075afe5988d169cb5c3a629aca","author":{"name":"KONRAD Frederic","email":"65d957747955457a3358fd7137262a55c9d81c70@greensocs.com"},"message":"cputlb: introduce tlb_flush_* async work.\n\nSome architectures allow to flush the tlb of other VCPUs. This is not a problem\nwhen we have only one thread for all VCPUs but it definitely needs to be an\nasynchronous work when we are in true multithreaded work.\n\nWe take the tb_lock() when doing this to avoid racing with other threads\nwhich may be invalidating TB's at the same time. The alternative would\nbe to use proper atomic primitives to clear the tlb entries en-mass.\n\nThis patch doesn't do anything to protect other cputlb function being\ncalled in MTTCG mode making cross vCPU changes.\n\nSigned-off-by: KONRAD Frederic <fred.konrad@greensocs.com>\n[AJB: remove need for g_malloc on defer, make check fixes, tb_lock]\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\nMessage-Id: <20161109145748.27282-12-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/9d5afb6dfd54c5075afe5988d169cb5c3a629aca"},{"sha":"29409379eaddbe20303b60ad7be03e7060146046","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"cputlb: tweak qemu_ram_addr_from_host_nofail reporting\n\nThis moves the helper function closer to where it is called and updates\nthe error message to report via error_report instead of the deprecated\nfprintf.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-13-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/29409379eaddbe20303b60ad7be03e7060146046"},{"sha":"3fa31588e4be0cd354db8fb318dfd6faa701e572","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"cputlb: atomically update tlb fields used by tlb_reset_dirty\n\nThe main use case for tlb_reset_dirty is to set the TLB_NOTDIRTY flags\nin TLB entries to force the slow-path on writes. This is used to mark\npage ranges containing code which has been translated so it can be\ninvalidated if written to. To do this safely we need to ensure the TLB\nentries in question for all vCPUs are updated before we attempt to run\nthe code otherwise a race could be introduced.\n\nTo achieve this we atomically set the flag in tlb_reset_dirty_range and\ntake care when setting it when the TLB entry is filled.\n\nThe helper function is made static as it isn't used outside of cputlb.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\nMessage-Id: <20161109145748.27282-14-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/3fa31588e4be0cd354db8fb318dfd6faa701e572"},{"sha":"6fd0c17d58f2233a847f71705ef4e08626a4de55","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target-arm/powerctl: defer cpu reset work to CPU context\n\nWhen switching a new vCPU on we want to complete a bunch of the setup\nwork before we start scheduling the vCPU thread. To do this cleanly we\ndefer vCPU setup to async work which will run the vCPUs execution\ncontext as the thread is woken up. The scheduling of the work will kick\nthe vCPU awake.\n\nThis avoids potential races in MTTCG system emulation.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-15-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/6fd0c17d58f2233a847f71705ef4e08626a4de55"},{"sha":"57cfc43345945a59d32f1669193749c1501204cf","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target-arm/cpu: don't reset TLB structures, use cputlb to do it\n\ncputlb owns the TLB entries and knows how to safely update them in\nMTTCG.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-16-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/57cfc43345945a59d32f1669193749c1501204cf"},{"sha":"9b07a0765b75b930a7a81dc2eb653f691429958b","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target-arm: ensure BQL taken for ARM_CP_IO register access\n\nMost ARMCPRegInfo structures just allow updating of the CPU field.\nHowever some have more complex operations that *may* be have cross vCPU\neffects therefor need to be serialised. The most obvious examples at the\nmoment are things that affect the GICv3 IRQ controller. To avoid\napplying this requirement to all registers with custom access functions\nwe check for if the type is marked ARM_CP_IO.\n\nBy default all MMIO access to devices already takes the BQL to serialise\nhardware emulation.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-17-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/9b07a0765b75b930a7a81dc2eb653f691429958b"},{"sha":"2d1f279377c1e7faf03148f368bc6b1d1e42ee51","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target-arm: helpers which may affect global state need the BQL\n\nAs the arm_call_el_change_hook may affect global state (for example with\nupdating the global GIC state) we need to assert/take the BQL.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-18-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/2d1f279377c1e7faf03148f368bc6b1d1e42ee51"},{"sha":"b53580b48358a8f06e2852dd2655a0cb0c09da8c","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"target-arm: don't generate WFE/YIELD calls for MTTCG\n\nThe WFE and YIELD instructions are really only hints and in TCG's case\nthey were useful to move the scheduling on from one vCPU to the next. In\nthe parallel context (MTTCG) this just causes an unnecessary cpu_exit\nand contention of the BQL.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-19-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/b53580b48358a8f06e2852dd2655a0cb0c09da8c"},{"sha":"92833783549cf3e974e13130dcc0eced29ace591","author":{"name":"Alex Bennée","email":"39f80399868a825be6587708c1426500fb9dbed0@linaro.org"},"message":"tcg: enable MTTCG by default for ARM on x86 hosts\n\nThis enables the multi-threaded system emulation by default for ARMv7\nand ARMv8 guests using the x86_64 TCG backend. This means:\n\n  - The x86_64 TCG backend supports cmpxchg based atomic ops\n  - The x86_64 TCG backend emits barriers for barrier ops\n\nAnd on the guest side:\n\n  - The ARM translate.c/translate-64.c have been converted to\n    - use MTTCG safe atomic primitives\n    - emit the appropriate barrier ops\n  - The ARM machine has been updated to\n    - hold the BQL when modifying shared cross-vCPU state\n    - defer cpu_reset to async safe work\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20161109145748.27282-20-alex.bennee@linaro.org>","distinct":false,"url":"https://api.github.com/repos/rth7680/qemu/commits/92833783549cf3e974e13130dcc0eced29ace591"}]}
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