{"push_id":1046398642,"size":78,"distinct_size":78,"ref":"refs/heads/master","head":"433ac20b17029077a77227d525dcf565100c9a1c","before":"de765686f8cfb9840def7e4aed2c7acf7c8a5a82","commits":[{"sha":"0fb615093137b8d9be26745da21126e6ddfce78a","author":{"email":"b907bf8ad5a0e7bf3e0b7632b5263b02521ee29e@gmail.com","name":"Sean Silva"},"message":"Fix case confusion.\n\nThe test case was defining and using a function 'notExported()', but\nthe FileCheck checks were checking for the name 'not_exported'. This\nchanges the test to use 'notExported' across the board. Also, the test\ndefined a function 'not_defined()', but doesn't have any checks related\nto it. For consistency, this name is changed to 'notDefined'. A later\ncommit will add checks for 'notDefined'.\n\nPatch by Warren Ristow!\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264984 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/0fb615093137b8d9be26745da21126e6ddfce78a"},{"sha":"dc6860fc8267e6046209498234b57adb8ce1bdac","author":{"email":"76a8e82c3bdc78a1f9490a34857cdee8b1b06a45@anl.gov","name":"Hal Finkel"},"message":"[PowerPC] Load two floats directly instead of using one 64-bit integer load\n\nWhen dealing with complex<float>, and similar structures with two\nsingle-precision floating-point numbers, especially when such things are being\npassed around by value, we'll sometimes end up loading both float values by\nextracting them from one 64-bit integer load. It looks like this:\n\n  t13: i64,ch = load<LD8[%ref.tmp]> t0, t6, undef:i64\n      t16: i64 = srl t13, Constant:i32<32>\n    t17: i32 = truncate t16\n  t18: f32 = bitcast t17\n    t19: i32 = truncate t13\n  t20: f32 = bitcast t19\n\nThe problem, especially before the P8 where those bitcasts aren't legal (and\nget expanded via the stack), is that it would have been better to use two\nfloating-point loads directly. Here we add a target-specific DAGCombine to do\njust that. In short, we turn:\n\n\tld 3, 0(5)\n\tstw 3, -8(1)\n\trldicl 3, 3, 32, 32\n\tstw 3, -4(1)\n\tlfs 3, -4(1)\n\tlfs 0, -8(1)\n\ninto:\n\n        lfs 3, 4(5)\n        lfs 0, 0(5)\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264988 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/dc6860fc8267e6046209498234b57adb8ce1bdac"},{"sha":"a528f3f7b73f2562ad82289fe69ba901abc10942","author":{"email":"1cd424918902c1dbc16c61ea09f30b31f6c2f0e9@freebsd.org","name":"Davide Italiano"},"message":"[DebugInfo] Subprograms should belong to a CU.\n\nStart fixing tests accordingly. There are still\nabout 35 failures before we can enable this check\nin the IR verifier.\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264990 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/a528f3f7b73f2562ad82289fe69ba901abc10942"},{"sha":"6c25a70663834d3a9e8e5902c9acc53b34dd83b2","author":{"email":"0c9ca018c303606191d06dd2c0bdf1206717c3f3@gmail.com","name":"Craig Topper"},"message":"[X86] Use MVT instead of EVT in code called after legalization.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264992 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/6c25a70663834d3a9e8e5902c9acc53b34dd83b2"},{"sha":"bf8c7c9a0d99ff03ed0c700083d34ebebfebb79e","author":{"email":"d72748a98fd8b476107003df407128e166d060ac@playingwithpointers.com","name":"Sanjoy Das"},"message":"[SCEV] NFC code motion to simplify later change\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264993 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/bf8c7c9a0d99ff03ed0c700083d34ebebfebb79e"},{"sha":"e840b37dc0843960037649825fa3ba17d93bbd48","author":{"email":"d72748a98fd8b476107003df407128e166d060ac@playingwithpointers.com","name":"Sanjoy Das"},"message":"[SCEV] Track NoWrap properties using MatchBinaryOp, NFC\n\nThis way once we teach MatchBinaryOp to map more things into arithmetic,\nthe non-wrapping add recurrence construction would understand it too.\nRight now MatchBinaryOp still only understands arithmetic, so this is\nsolely a code-reorganization change.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264994 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/e840b37dc0843960037649825fa3ba17d93bbd48"},{"sha":"2b00aae5c0bf16c681f7542e06d235426003c8e9","author":{"email":"d72748a98fd8b476107003df407128e166d060ac@playingwithpointers.com","name":"Sanjoy Das"},"message":"Delete trailing whitespace\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264995 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/2b00aae5c0bf16c681f7542e06d235426003c8e9"},{"sha":"0d31c7f6c6991d89f4443749ba21df4d036d97ae","author":{"email":"d72748a98fd8b476107003df407128e166d060ac@playingwithpointers.com","name":"Sanjoy Das"},"message":"[InstCombine] Fix incorrect rule from rL236202\n\nThe rule for SMIN introduced in rL236202 doesn't work as advertised: the\ncheck for Pred == ICmpInst::ICMP_SGT was missing.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264996 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/0d31c7f6c6991d89f4443749ba21df4d036d97ae"},{"sha":"0bfce3885d204dd4cb113f6b48c3ca1be726d446","author":{"email":"e9dd64ab86c0554d416df05e532621e689f9b261@linux.vnet.ibm.com","name":"Jonas Paulsson"},"message":"Indentation fix in SystemZInstrInfo.cpp\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265000 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/0bfce3885d204dd4cb113f6b48c3ca1be726d446"},{"sha":"12c0e3a87fb2404a32aafddecca90075b86ad93b","author":{"email":"845dfb253b44f3c1b7a81c92ce834192f783cf87@imperial.ac.uk","name":"Jeroen Ketema"},"message":"Silence warnings in OCaml bindings\n\n* LLVMDisposeMessage lives in llvm-c/Core.h, include this file where necessary\n* LLVMAddTargetData has been removed, follow suit in the bindings\n\nDifferential Revision: http://reviews.llvm.org/D18633\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265001 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/12c0e3a87fb2404a32aafddecca90075b86ad93b"},{"sha":"4e6485e747b004473be2dcdf69ecef8bdc2cc8da","author":{"email":"ceadf621e01489dc9705a269a331fb3c9fbbaef3@imgtec.com","name":"Zlatko Buljan"},"message":"[mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions\nDifferential Revision: http://reviews.llvm.org/D17334\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265002 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/4e6485e747b004473be2dcdf69ecef8bdc2cc8da"},{"sha":"638cd0356dc0cc8a184191703481f0d5adf2877f","author":{"email":"ea91796269c7842d401af30276638d4aaa593379@googlemail.com","name":"Benjamin Kramer"},"message":"[TTI] Let the cost model estimate ctpop costs based on legality\n\nPPC has a vector popcount, this lets the vectorizer use the correct cost\nfor it. Tweak X86 test to use an intrinsic that's actually scalarized (we\nhave a somewhat efficient lowering for vector popcount using SSE, the\ncost model finds that now).\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265005 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/638cd0356dc0cc8a184191703481f0d5adf2877f"},{"sha":"8cd0a25bf452773abe20b05d608b7fb6b30ab719","author":{"email":"157f0aa387af74e0e19b139f9b56b9a20fc05454@imgtec.com","name":"Daniel Sanders"},"message":"[mips] Range check simm9 and fix a bug this revealed.\n\nSummary:\nThe bug was that microMIPS's [ls]w[lr]e instructions claimed to support a\n12-bit offset when it is only 9-bit.\n\nReviewers: vkalintiris\n\nSubscribers: llvm-commits, dsanders\n\nDifferential Revision: http://reviews.llvm.org/D18434\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265010 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/8cd0a25bf452773abe20b05d608b7fb6b30ab719"},{"sha":"9daabaed604688f209efbbea78cca413f51be149","author":{"email":"110b37d45ddda9f73d754416365dfae63927f12d@google.com","name":"Nirav Dave"},"message":"Prevent X86ISelLowering from merging volatile loads\n\nChange isConsecutiveLoads to check that loads are non-volatile as this\nis a requirement for any load merges. Propagate change to two callers.\n\nReviewers: RKSimon\n\nSubscribers: llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D18546\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265013 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/9daabaed604688f209efbbea78cca413f51be149"},{"sha":"2693fe3c51798c152da017698fdc28166d39f1a1","author":{"email":"157f0aa387af74e0e19b139f9b56b9a20fc05454@imgtec.com","name":"Daniel Sanders"},"message":"[mips] Split mem_msa into range checked mem_simm10 and mem_simm10_lsl[123]\n\nSummary:\nAlso, made test_mi10.s formatting consistent with the majority of the\nMC tests.\n\nReviewers: vkalintiris\n\nSubscribers: dsanders, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D18435\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265014 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/2693fe3c51798c152da017698fdc28166d39f1a1"},{"sha":"8fef4bc756eee583c9b8f855e953e45ec1dbc0a9","author":{"email":"f097b54fe41e5519a99d9a0e622d94e29f2c380e@amd.com","name":"Sam Kolton"},"message":"[AMDGPU] Disassembler: support for DPP\n\nReview: http://reviews.llvm.org/D18642\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265015 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/8fef4bc756eee583c9b8f855e953e45ec1dbc0a9"},{"sha":"dc022bad272091674be4628268637b984a0ab3dd","author":{"email":"9acf675a17b6024352055090bee135712207e3d8@gmail.com","name":"Dmitry Polukhin"},"message":"[IFUNC] Introduce GlobalIndirectSymbol as a base class for alias and ifunc\n\nThis patch is a part of http://reviews.llvm.org/D15525\n\nGlobalIndirectSymbol class contains common implementation for both\naliases and ifuncs. This patch should be NFC change that just prepare\ncommon code for ifunc support.\n\nDifferential Revision: http://reviews.llvm.org/D18433\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265016 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/dc022bad272091674be4628268637b984a0ab3dd"},{"sha":"15d116ada70a33139955eaed5f93f8755805a172","author":{"email":"157f0aa387af74e0e19b139f9b56b9a20fc05454@imgtec.com","name":"Daniel Sanders"},"message":"[mips] Range check simm11 and mem_simm11.\n\nSummary:\nldc2/sdc2 now emit slightly worse diagnostics for MIPS-I. The problem\nis that they don't trigger the custom parser because all the candidates\nare disabled by feature bits. On all other subtargets, the diagnostics are\naccurate but are subject to the usual issues of needing to report multiple\nways to correct the code (e.g. smaller offset, enable a CPU feature) but\nonly being able to report one error.\n\nReviewers: vkalintiris\n\nSubscribers: dsanders, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D18436\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265018 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/15d116ada70a33139955eaed5f93f8755805a172"},{"sha":"2fcdb70af7cdfaa9e131d7a2d82ed8024d5e9e22","author":{"email":"157f0aa387af74e0e19b139f9b56b9a20fc05454@imgtec.com","name":"Daniel Sanders"},"message":"[mips] Range check simm16\n\nSummary:\nThere are too many instructions to exhaustively test so addiu and lwc2 are\nused as representative examples.\n\nIt should be noted that many memory instructions that should have simm16\nrange checking do not because it is also necessary to support the macro\nof the same name which accepts simm32. The range checks for these occur in\nthe macro expansion.\n\nReviewers: vkalintiris\n\nSubscribers: dsanders, llvm-commits\n\nDifferential Revision: http://reviews.llvm.org/D18437\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265019 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/2fcdb70af7cdfaa9e131d7a2d82ed8024d5e9e22"},{"sha":"ca50bf5da15487d533765e16dd82ce28b63a911f","author":{"email":"dfbb67861321c3a0b65599ad75850a0b877f5c0d@de.ibm.com","name":"Ulrich Weigand"},"message":"[PowerPC] Remove incorrect use of COPY_TO_REGCLASS in fast isel\n\nThe fast isel pass currently emits a COPY_TO_REGCLASS node to convert\nfrom a F4RC to a F8RC register class during conversion of a\nfloating-point number to integer. There is actually no support in the\ncommon code instruction printers to emit COPY_TO_REGCLASS nodes, so the\nPowerPC back-end has special code there to simply ignore\nCOPY_TO_REGCLASS.\n\nThis is correct *if and only if* the source and destination registers of\nCOPY_TO_REGCLASS are the same (except for the different register class).\nBut nothing guarantees this to be the case, and if the register\nallocator does end up allocating source and destination to different\nregisters after all, the back-end simply generates incorrect code. I've\nincluded a test case that shows such incorrect code generation.\n\nHowever, it seems that COPY_TO_REGCLASS is actually not intended to be\nused at the MI layer at all. It is used during SelectionDAG, but always\nlowered to a plain COPY before emitting MI. Other back-end's fast isel\npasses never emit COPY_TO_REGCLASS at all. I suspect it is simply wrong\nfor the PowerPC back-end to emit it here.\n\nThis patch changes the PowerPC back-end to directly emit COPY instead of\nCOPY_TO_REGCLASS and removes the special handling in the instruction\nprinters.\n\nDifferential Revision: http://reviews.llvm.org/D18605\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265020 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":true,"url":"https://api.github.com/repos/J-Liu/llvm/commits/ca50bf5da15487d533765e16dd82ce28b63a911f"}]}