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This support is disabled by default on all targets and any target\nthat has support for this type is free to add it.\n\nBased on feedback that I've received from target maintainers, this appears to\nbe the right thing for most targets. I have not heard from the maintainers of\nX86 which I believe supports this type. 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All functions are annotated with nothrow and pure attribute, which enables better optimization.\n\nPatch by Taewook Oh.\n\ngit-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@266199 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/yxsamliu/clang/commits/9c7fd406fcd23502fc5746b7ff03711ed81c90bd"},{"sha":"3aa971124d4739bdbe69079c6cc367a621f6ce4c","author":{"name":"Aaron Ballman","email":"0ea57831a6aee87faae8cf48eb3fed040f8dc3de@aaronballman.com"},"message":"Reverting r266199; it causes build bot failures.\n\nhttp://lab.llvm.org:8011/builders/clang-s390x-linux/builds/3255\nhttp://lab.llvm.org:8011/builders/clang-ppc64be-linux/builds/3517  \n\ngit-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@266201 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/yxsamliu/clang/commits/3aa971124d4739bdbe69079c6cc367a621f6ce4c"},{"sha":"5c9054ef6f4b6003f525108ca3039c65433b0463","author":{"name":"Michael Zuckerman","email":"bab4cdb6965828c3a21d9303f80f819ce8affda9@intel.com"},"message":"[Clang][AVX512][Builtin] Adding support to intrinsics of pmovs{d|q}{b|w|d}{128|256|512} instruction set\n\nDifferential Revision: http://reviews.llvm.org/D19023\n\n\n\ngit-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@266202 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/yxsamliu/clang/commits/5c9054ef6f4b6003f525108ca3039c65433b0463"},{"sha":"11b940607f9dab3090ae05f268c2815d9f60bf87","author":{"name":"Tim Northover","email":"f2f324cbf35679814b7526a760f2841b68589222@apple.com"},"message":"ARM: make Darwin's \"-arch armv7em\" default to hard-float.\n\nWe've already paid the price for separate \"armv7m\" and \"armv7em\" slices\n(support in other tools), it's silly to make them identical other than the\ndefault CPU.\n\nrdar://23055688\n\ngit-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@266211 91177308-0d34-0410-b5e6-96231b3b80d8","distinct":false,"url":"https://api.github.com/repos/yxsamliu/clang/commits/11b940607f9dab3090ae05f268c2815d9f60bf87"},{"sha":"4329eca357ee23753ccf00c9c0602d216739dee9","author":{"name":"Tim Northover","email":"f2f324cbf35679814b7526a760f2841b68589222@apple.com"},"message":"AArch64: allow 64-bit access to sysregs.\n\nAlthough all the registers are actually 32-bits, I think we have to assume the\nhigh 32-bits could be RES0 (the ARM ARM is unclear). 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