{"push_id":1118543315,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"7f637af2bd537f427b4c3b153e49b509a459c35f","before":"f2fd12cc32f3d6bfe4cd86d3b18bd090637123a2","commits":[{"sha":"7f637af2bd537f427b4c3b153e49b509a459c35f","author":{"email":"c464ed312fa6f818297227c7e5018fc9f4bd95ad@synopsys.com","name":"Chuck Jordan"},"message":"spi: For spi_dw, added SPI_DW_FIFO_DEPTH as configurable paramter\n\nWhen using the Synopsys DesignWare Synchronous Serial Interface (SSI),\nthe FIFO depth can vary from 2-256, depending upon how this module is built.\nFor quark_se_ss, it was using a depth of 8. For EM Starterkit, it will be\n32. Adding this now as a configurable option. A larger FIFO really helps\nreduce SPI interrupts.\n\nChange-Id: Id2bc8470bfc08ab447d38b89c7904cff010c63bd\nSigned-off-by: Chuck Jordan <cjordan@synopsys.com>","distinct":true,"url":"https://api.github.com/repos/kraj/zephyr/commits/7f637af2bd537f427b4c3b153e49b509a459c35f"}]}