{"push_id":1441594925,"size":531,"distinct_size":531,"ref":"refs/heads/master","head":"0faacf729185baaeb7f01ea67d9a2691b648a3ab","before":"d63597fc1d8b3ad0aee551791e9dc8e61f2596ef","commits":[{"sha":"c5a654786b5b68c5c215e3bd1bc83b02d7e2a0e9","author":{"name":"Ilia Mirkin","email":"b2ef0ae728ba642680a7b0ef24aed39533e21358@alum.mit.edu"},"message":"swr: [rasterizer memory] minify original sizes for block formats\n\nThere's no guarantee that mip width/height will be a multiple of the\ncompressed block size. Doing a divide by the block size first yields\ndifferent results than GL expects, so we do the divide at the end.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Tim Rowley <timothy.o.rowley@intel.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/c5a654786b5b68c5c215e3bd1bc83b02d7e2a0e9"},{"sha":"ee0b6597a9579342029e46bf2bc4a8dd887f7896","author":{"name":"Ilia Mirkin","email":"b2ef0ae728ba642680a7b0ef24aed39533e21358@alum.mit.edu"},"message":"swr: [rasterizer memory] minify texture width before alignment\n\nThe minification should happen before alignment, not after. See similar\nlogic on ComputeLODOffsetY. The current logic requires unnecessarily\nlarge textures when there's an initial NPOT size.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Tim Rowley <timothy.o.rowley@intel.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/ee0b6597a9579342029e46bf2bc4a8dd887f7896"},{"sha":"16d42f2f3dcc8bec8d75b53d1e9e9cf5af6e528c","author":{"name":"Ilia Mirkin","email":"b2ef0ae728ba642680a7b0ef24aed39533e21358@alum.mit.edu"},"message":"swr: call swr_update_derived unconditionally when drawing/clearing\n\nCurrently a sequence like draw/map/draw/map will cause the second map to\nnot wait for the second draw. This is because the first map will clear\nthe resource business bit, and the second draw won't reset it since no\nstate has changed.\n\nswr_update_derived does a tiny bit of extra work, including updating the\nSWR_BACKEND_STATE as well as waiting for prending fences. If that's a\nproblem, we could call swr_update_resource_status directly from\ndraw/clear handlers.\n\nFixes clearbuffer-stencil, clearbuffer-depth, clearbuffer-depth-stencil,\nand clearbuffer-display-lists.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/16d42f2f3dcc8bec8d75b53d1e9e9cf5af6e528c"},{"sha":"d48740568faff4aad78a46c67f73ea3c5ea3bd0c","author":{"name":"Ilia Mirkin","email":"b2ef0ae728ba642680a7b0ef24aed39533e21358@alum.mit.edu"},"message":"swr: allocate all scratch space in one go for vertex buffers\n\nMultiple buffers may reference client arrays. When this happens, we\nmight reach for scratch space multiple times, which could cause later\narrays to invalidate the pointers allocated for the earlier ones.\n\nThis fixes copyteximage 2D_ARRAY.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/d48740568faff4aad78a46c67f73ea3c5ea3bd0c"},{"sha":"c3dd5b2e3f47f23c8f6651e0d3af6fde7486656d","author":{"name":"Ilia Mirkin","email":"b2ef0ae728ba642680a7b0ef24aed39533e21358@alum.mit.edu"},"message":"swr: don't claim to allow setting layer/viewport from VS\n\nThis may ultimately be possible to support, but for now it's not hooked\nup and the swr core only supports this output from GS.\n\nThis normally wouldn't matter, but we lie about supporting GL 3.2, and\nalso the blitter and st/mesa will make use of this functionality if\nclaimed.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Tim Rowley <timothy.o.rowley@intel.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/c3dd5b2e3f47f23c8f6651e0d3af6fde7486656d"},{"sha":"807bc6ea9ee60240b44ca906e875f23d6e4f0ef7","author":{"name":"Ilia Mirkin","email":"b2ef0ae728ba642680a7b0ef24aed39533e21358@alum.mit.edu"},"message":"swr: calculate viewport width/height based on the scale\n\nThe former calculations were for min/max y. The width/height don't take\ntranslate into account.\n\nSigned-off-by: Ilia Mirkin <imirkin@alum.mit.edu>\nReviewed-by: Tim Rowley <timothy.o.rowley@intel.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/807bc6ea9ee60240b44ca906e875f23d6e4f0ef7"},{"sha":"581bd1d12a0c8f68110519196673b11940887143","author":{"name":"Timothy Arceri","email":"2ddafe7dbd3e23500c275f83e0c6a411ad072887@collabora.com"},"message":"glsl: fix NULL check\n\nFixes copy and paste error in 9d96d3803ab","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/581bd1d12a0c8f68110519196673b11940887143"},{"sha":"43ee4917cadbba7677def091333edbf3cf069f8a","author":{"name":"Bas Nieuwenhuizen","email":"99bb905c4f884bf38b04075a0f5da8a4fd0bd599@basnieuwenhuizen.nl"},"message":"radv: Store UUID in physical device.\n\nNo sense in repeatedly determining it. Also, it might be dependent\non the device as shaders get compiled differently for SI/CIK/VI etc.\n\nSigned-off-by: Bas Nieuwenhuizen <basni@google.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/43ee4917cadbba7677def091333edbf3cf069f8a"},{"sha":"d94383970f2cad9f474760b18fd277efeda4c612","author":{"name":"Bas Nieuwenhuizen","email":"99bb905c4f884bf38b04075a0f5da8a4fd0bd599@basnieuwenhuizen.nl"},"message":"radv: Use library mtime for cache UUID.\n\nWe want to also invalidate the cache when LLVM gets changed. As the\nspecific LLVM revision is not fixed at build time, we will need to\ncheck at runtime. Computing a checksum for LLVM is going to be very\nexpensive, so just use the mtime.\n\nTested on my computer that the returned DSO for the LLVM symbol is\nactually the LLVM DSO.\n\nSigned-off-by: Bas Nieuwenhuizen <basni@google.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/d94383970f2cad9f474760b18fd277efeda4c612"},{"sha":"24427e31ef5949ded323ae193f0e414417972c17","author":{"name":"Bas Nieuwenhuizen","email":"99bb905c4f884bf38b04075a0f5da8a4fd0bd599@basnieuwenhuizen.nl"},"message":"radv: Incorporate GPU family into cache UUID.\n\nInvalidates the cache when someone switches cards.\n\nSigned-off-by: Bas Nieuwenhuizen <basni@google.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/24427e31ef5949ded323ae193f0e414417972c17"},{"sha":"fa57b771059efb4c409253c75a42785105ba67fa","author":{"name":"Dave Airlie","email":"bb4fc8ee23048f808a4e317631d81d4f55a4e4cb@redhat.com"},"message":"radv/meta: cleanup resolve vertex state emission\n\nFor the hw resolve there is no need to emit any sort\nof texture coordinates, so drop them all in the meta path.\n\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nSigned-off-by: Dave Airlie <airlied@redhat.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/fa57b771059efb4c409253c75a42785105ba67fa"},{"sha":"5697cfb7ec08e827a48adc2cd34364696e209147","author":{"name":"Dave Airlie","email":"bb4fc8ee23048f808a4e317631d81d4f55a4e4cb@redhat.com"},"message":"radv/ac: cleanup ddxy emission\n\nThis cleans up the ddxy emission along the same lines as\nradeonsi. It also means we don't use LDS on VI chips we\nuse the dspermute interface, it also removes some duplicated\ncode.\n\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nSigned-off-by: Dave Airlie <airlied@redhat.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/5697cfb7ec08e827a48adc2cd34364696e209147"},{"sha":"3c6151ccafeb47febb8320b7f4f7bbc0e819708e","author":{"name":"Dave Airlie","email":"bb4fc8ee23048f808a4e317631d81d4f55a4e4cb@redhat.com"},"message":"radv/ac: add implementation of load_sample_pos intrinsic.\n\nThis fixes a bunch of crashes in CTS tests looking for this.\n\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nSigned-off-by: Dave Airlie <airlied@redhat.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/3c6151ccafeb47febb8320b7f4f7bbc0e819708e"},{"sha":"220912e21432dba996cb2694dea480c65cf6a7c6","author":{"name":"Dave Airlie","email":"bb4fc8ee23048f808a4e317631d81d4f55a4e4cb@redhat.com"},"message":"radv: fix sample id loading\n\nThe sample id is packed into bits 8-12, so adjust\nthings properly.\n\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nSigned-off-by: Dave Airlie <airlied@redhat.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/220912e21432dba996cb2694dea480c65cf6a7c6"},{"sha":"f395e3445df98b0398865a1897bca003f9add6f4","author":{"name":"Dave Airlie","email":"bb4fc8ee23048f808a4e317631d81d4f55a4e4cb@redhat.com"},"message":"radv: add support for shader stats dump\n\nI've started working on a shader-db alike for Vulkan,\nit's based on vktrace and it records pipelines, this\nadds support to dump the shader stats exactly like\nradeonsi does, so I can reuse the shader-db scripts it\nuses.\n\nReviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>\nSigned-off-by: Dave Airlie <airlied@redhat.com>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/f395e3445df98b0398865a1897bca003f9add6f4"},{"sha":"663b2e9a92f152c314f611526b8a16ff4c06249f","author":{"name":"Kenneth Graunke","email":"e8e0e12ced052a7b04539107b6dfbe9787d38bd2@whitecape.org"},"message":"nir: Add a \"compact array\" flag and IO lowering code.\n\nCertain built-in arrays, such as gl_ClipDistance[], gl_CullDistance[],\ngl_TessLevelInner[], and gl_TessLevelOuter[] are specified as scalar\narrays.  Normal scalar arrays are sparse - each array element usually\noccupies a whole vec4 slot.  However, most hardware assumes these\nbuilt-in arrays are tightly packed.\n\nThe new var->data.compact flag indicates that a scalar array should\nbe tightly packed, so a float[4] array would take up a single vec4\nslot, and a float[8] array would take up two slots.\n\nThey are still arrays, not vec4s, however.  nir_lower_io will generate\nintrinsics using ARB_enhanced_layouts style component qualifiers.\n\nv2: Add nir_validate code to enforce type restrictions.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/663b2e9a92f152c314f611526b8a16ff4c06249f"},{"sha":"9a179f2db090bfb5643779ac84c2b61fe525a780","author":{"name":"Kenneth Graunke","email":"e8e0e12ced052a7b04539107b6dfbe9787d38bd2@whitecape.org"},"message":"nir: add a pass to compact clip/cull distances.\n\nv2: Use nir_is_per_vertex_io() rather than is_arrays_of_arrays().\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/9a179f2db090bfb5643779ac84c2b61fe525a780"},{"sha":"a9eabd539cf75f8e0e0c1c012a7f5e666304dd9e","author":{"name":"Kenneth Graunke","email":"e8e0e12ced052a7b04539107b6dfbe9787d38bd2@whitecape.org"},"message":"anv: Combine ClipDistance and CullDistance arrays.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/a9eabd539cf75f8e0e0c1c012a7f5e666304dd9e"},{"sha":"7471bb5fa49914673f2764360427d8dc1e63b9a4","author":{"name":"Kenneth Graunke","email":"e8e0e12ced052a7b04539107b6dfbe9787d38bd2@whitecape.org"},"message":"anv: Set clip/cull distances fields in packets.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/7471bb5fa49914673f2764360427d8dc1e63b9a4"},{"sha":"536af43fe3fafc728a8a790692be197c38213721","author":{"name":"Kenneth Graunke","email":"e8e0e12ced052a7b04539107b6dfbe9787d38bd2@whitecape.org"},"message":"spirv: Silence unsupported capability warnings for Clip/CullDistance.\n\nSigned-off-by: Kenneth Graunke <kenneth@whitecape.org>\nReviewed-by: Jason Ekstrand <jason@jlekstrand.net>","distinct":true,"url":"https://api.github.com/repos/iXit/Mesa-3D/commits/536af43fe3fafc728a8a790692be197c38213721"}]}
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