{"action":"opened","issue":{"url":"https://api.github.com/repos/ucb-bar/firrtl/issues/65","repository_url":"https://api.github.com/repos/ucb-bar/firrtl","labels_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/65/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/65/comments","events_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/65/events","html_url":"https://github.com/ucb-bar/firrtl/issues/65","id":135657505,"number":65,"title":"No Support for Zero-width wires","user":{"login":"jackkoenig","id":8584418,"avatar_url":"https://avatars.githubusercontent.com/u/8584418?v=3","gravatar_id":"","url":"https://api.github.com/users/jackkoenig","html_url":"https://github.com/jackkoenig","followers_url":"https://api.github.com/users/jackkoenig/followers","following_url":"https://api.github.com/users/jackkoenig/following{/other_user}","gists_url":"https://api.github.com/users/jackkoenig/gists{/gist_id}","starred_url":"https://api.github.com/users/jackkoenig/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jackkoenig/subscriptions","organizations_url":"https://api.github.com/users/jackkoenig/orgs","repos_url":"https://api.github.com/users/jackkoenig/repos","events_url":"https://api.github.com/users/jackkoenig/events{/privacy}","received_events_url":"https://api.github.com/users/jackkoenig/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"milestone":null,"comments":0,"created_at":"2016-02-23T07:14:27Z","updated_at":"2016-02-23T07:14:27Z","closed_at":null,"body":"See bug fix in b487ab24c0e298e7781f74811b8bfcd24384d1b5\r\nThis was due to rocket regression having memory of depth = 1, thus address width = 0. This makes sense because the address port is unnecessary in this case.\r\n\r\nIf I recall correctly, support for zero-width wires was mentioned as future work? But if they are supported in Chisel, I think it should be now work."}}