{"push_id":930154775,"size":2,"distinct_size":2,"ref":"refs/heads/master","head":"37ecabf765774df21cf900daf9c2d0d3c78c537c","before":"d5fd6eda08b657c2e916bb3b185f36c70f43feba","commits":[{"sha":"54c8d2ca8b99c27761b45f35cd17f79512cb4a23","author":{"email":"3ff39c994a7983474a41a8ae0a0af3e9c67ba4d5@adacore.com","name":"Tristan Gingold"},"message":"st-util: synchronize cache for stm32f7\n\nThis patch handles the cache on the cortex-m7 stm32f7 cpu.\nWhen gdb inserts a soft breakpoint (which is the default for\ncode in RAM), it replaces an instruction with a breakpoint\ninstruction.  But if the caches are enabled, the replacement\nmay be made only in the D-cache.  To reach the I-cache, the\nD-cache must be flushed and the I-cache invalidated.\n\nThis implementation is coarse: it cleans the whole D-cache\nand invalidate the whole I-cache.  It is possible to\ntrack which cache lines have to be cleaned and invalidated.","distinct":true,"url":"https://api.github.com/repos/texane/stlink/commits/54c8d2ca8b99c27761b45f35cd17f79512cb4a23"},{"sha":"37ecabf765774df21cf900daf9c2d0d3c78c537c","author":{"email":"02c31dffce478cf72731be1ae674421087642566@gmail.com","name":"texane"},"message":"Merge pull request #363 from gingold-adacore/cache\n\nst-util: synchronize cache for stm32f7","distinct":true,"url":"https://api.github.com/repos/texane/stlink/commits/37ecabf765774df21cf900daf9c2d0d3c78c537c"}]}