{"action":"opened","issue":{"url":"https://api.github.com/repos/m-labs/sayma/issues/35","repository_url":"https://api.github.com/repos/m-labs/sayma","labels_url":"https://api.github.com/repos/m-labs/sayma/issues/35/labels{/name}","comments_url":"https://api.github.com/repos/m-labs/sayma/issues/35/comments","events_url":"https://api.github.com/repos/m-labs/sayma/issues/35/events","html_url":"https://github.com/m-labs/sayma/issues/35","id":185951344,"number":35,"title":"analog mezzanine power/IO specification","user":{"login":"dhslichter","id":9222487,"avatar_url":"https://avatars.githubusercontent.com/u/9222487?v=3","gravatar_id":"","url":"https://api.github.com/users/dhslichter","html_url":"https://github.com/dhslichter","followers_url":"https://api.github.com/users/dhslichter/followers","following_url":"https://api.github.com/users/dhslichter/following{/other_user}","gists_url":"https://api.github.com/users/dhslichter/gists{/gist_id}","starred_url":"https://api.github.com/users/dhslichter/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/dhslichter/subscriptions","organizations_url":"https://api.github.com/users/dhslichter/orgs","repos_url":"https://api.github.com/users/dhslichter/repos","events_url":"https://api.github.com/users/dhslichter/events{/privacy}","received_events_url":"https://api.github.com/users/dhslichter/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":0,"created_at":"2016-10-28T15:23:46Z","updated_at":"2016-10-28T15:23:46Z","closed_at":null,"body":"Splitting out from #8.  Current specification:\r\n\r\n## Power rails\r\n\r\n- +12VDC @ 200 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth\r\n- +6VDC @ 1.5 A, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth\r\n- -12VDC @ 50 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth\r\n- -6VDC @ 150 mA, max 1 mV p-p noise in 20 Hz-20 MHz bandwidth\r\n- no switching \"spikes\" on rails\r\n- pi filters on all power lines\r\n    - 0402 NP0 1 nF cap (16V min rating) parallel 0805 X7R 10 uF cap (16V min rating - Samsung CL21B106KOQNNN or equivalent DC bias performance -- degrades to 7.5 uF @ 3.3V, 5.5 uF @ 6V, 2.7 uF @ 12V) to ground, between mezzanine and choke\r\n    - BLM41PG181SN1L choke\r\n    - 0805 X7R 10 uF cap to ground (16V min rating - Samsung CL21B106KOQNNN or equivalent DC bias performance), between choke and supply\r\n- desired supply voltages to be generated from these rails on mezzanine with dedicated LDOs\r\n- no switching supplies on mezzanines\r\n- +3.3VDC @ 1 A for digital-only devices on mezzanine.  Should still be filtered on Sayma to minimize noise. max 10 mV p-p noise in 20 Hz-20 MHz bandwidth acceptable.\r\n- single shared ground for analog and digital, connected to all SMP shields and all ground pins of power/IO connector\r\n\r\n\r\n## Power/IO header routing\r\n\r\n- as shown in image below from @gkasprow with exceptions listed below\r\n- power line filters to pi filters as described above.  \r\n- digital lines IO0-IO15 3.3V LVCMOS\r\n- I2C SDA/SCL (3.3V), pullup resistors to +3.3V installed on Sayma.  I2C fed from I2C mux chips on Sayma card.  Easy/compact level shifting on mezzanines (if needed) using discrete MOSFETs: http://www.nxp.com/documents/application_note/AN10441.pdf\r\n- digital IO are general purpose in hardware, but for SPI preferred pinout is:\r\n    - SCLK = IO0\r\n    - MOSI = IO1\r\n    - MISO = IO2\r\n    - CS = IO3\r\n    - additional chip selects starting with IO4 and up\r\n- power rails as shown (7V rail is actually 6V)\r\n- -6VDC rail not shown\r\n- 4x connections to slow ADC (24-bit sigma-delta) for drift/temp/etc monitoring.  ADC chip is mounted on  See #11.\r\n\r\n![image](https://cloud.githubusercontent.com/assets/9222487/19248583/342c2786-8eee-11e6-9b3d-df31b5e45433.png)\r\n"}}
{"actor":{"display_login":"dhslichter"}}