{"push_id":1354235784,"size":27,"distinct_size":27,"ref":"refs/heads/android-exynos5420-sec","head":"2ab2968d474d222adef2932cb84508204abb9672","before":"44aa824e2b88380e841d6b6fcc6eedb0d8cd104a","commits":[{"sha":"f100f6efbf34053b7c88dc885fbb9b04c4ce140a","author":{"name":"Arjun.K.V","email":"14b38ea43cfece34f8e1f0aaf519cfbc19235537@samsung.com"},"message":"PM: qos: Add DEVICE and BUS throughput\n\nAdds BUS and DEVICE qos classes so that Devfreq can use\nthese schemes.\n\nBUG=chrome-os-partner:19585\nTEST=Boot on Peach and check that there are no error messages\nfrom devfreq.\ncat /sys/devices/platform/exynos5420-devfreq-int/\ndevfreq/exynos5420-devfreq-int/time_in_state/int_time_in_state\n600000 0\n500000 0\n400000 0\n333000 885\n222000 20\n111000 11486\n83000 0\n\nAlso see that the voltage varies according to the\nlevels with power measurement equipment.\nChange-Id: If192d8a935abd5c83fb2fa568f93492e9abaa779\nSigned-off-by: Arjun.K.V <arjun.kv@samsung.com>\nReviewed-on: https://gerrit.chromium.org/gerrit/57913\nCommit-Queue: Andrew Bresticker <abrestic@chromium.org>\nReviewed-by: Andrew Bresticker <abrestic@chromium.org>\nTested-by: Andrew Bresticker <abrestic@chromium.org>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/f100f6efbf34053b7c88dc885fbb9b04c4ce140a"},{"sha":"c290f55299f67d16433055067021a003ec759ed9","author":{"name":"Stephen Boyd","email":"496892c5e989e3d4519358ac44c914f60a4d59d9@codeaurora.org"},"message":"ARM: sched_clock: Load cycle count after epoch stabilizes\n\nThere is a small race between when the cycle count is read from\nthe hardware and when the epoch stabilizes. Consider this\nscenario:\n\n CPU0                           CPU1\n ----                           ----\n cyc = read_sched_clock()\n cyc_to_sched_clock()\n                                 update_sched_clock()\n                                  ...\n                                  cd.epoch_cyc = cyc;\n  epoch_cyc = cd.epoch_cyc;\n  ...\n  epoch_ns + cyc_to_ns((cyc - epoch_cyc)\n\nThe cyc on cpu0 was read before the epoch changed. But we\ncalculate the nanoseconds based on the new epoch by subtracting\nthe new epoch from the old cycle count. Since epoch is most likely\nlarger than the old cycle count we calculate a large number that\nwill be converted to nanoseconds and added to epoch_ns, causing\ntime to jump forward too much.\n\nFix this problem by reading the hardware after the epoch has\nstabilized.\n\nSigned-off-by: Stephen Boyd <sboyd@codeaurora.org>\nSigned-off-by: Vidir Alexander Jonsson <valex@valex.is>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/c290f55299f67d16433055067021a003ec759ed9"},{"sha":"8548797af5118e48d190b05b484b0ca7b2a2b6c5","author":{"name":"Konstantin Khlebnikov","email":"d98af944b28c237d03a1da7acd8977cf98ecca58@samsung.com"},"message":"ARM: check stack pointer in get_wchan\n\nget_wchan() is lockless. Task may wakeup at any time and change its own stack,\nthus each next stack frame may be overwritten and filled with random stuff.\n\n/proc/$pid/stack interface had been disabled for non-current tasks, see [1]\nBut 'wchan' still allows to trigger stack frame unwinding on volatile stack.\n\nThis patch fixes oops in unwind_frame() by adding stack pointer validation on\neach step (as x86 code do), unwind_frame() already checks frame pointer.\n\nAlso I've found another report of this oops on stackoverflow (irony).\n\nSigned-off-by: Konstantin Khlebnikov <k.khlebnikov@samsung.com>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/8548797af5118e48d190b05b484b0ca7b2a2b6c5"},{"sha":"9887fffd484d433ba1443bf4635c93400b82e5f3","author":{"name":"Konstantin Khlebnikov","email":"d98af944b28c237d03a1da7acd8977cf98ecca58@samsung.com"},"message":"ARM: fix framepointer check in unwind_frame\n\nThis patch fixes corner case when (fp + 4) overflows unsigned long,\nfor example: fp = 0xFFFFFFFF -> fp + 4 == 3.\n\nSigned-off-by: Konstantin Khlebnikov <k.khlebnikov@samsung.com>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/9887fffd484d433ba1443bf4635c93400b82e5f3"},{"sha":"dc67132e57ffd24948e17af7a4b54a54303b4590","author":{"name":"Catalin Marinas","email":"6aa257b0f6444d48b36b727fdf3f5c1074b85fd0@arm.com"},"message":"arm: Enable IRQs before attempting to read user space in\n\nThe Undef abort handler in the kernel reads the undefined instruction\nfrom user space. If the page table was modified from another CPU, the\nuser access could fail and do_page_fault() will be executed with\ninterrupts disabled. This can potentially deadlock on ARM11MPCore or on\nCortex-A15 with erratum 798181 workaround enabled (both implying IPI for\nTLB maintenance with page table lock held).\n\nThis patch enables the IRQs in __und_usr before attempting to read the\ninstruction from user space.\n\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Vidir Alexander Jonsson <valex@valex.is>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/dc67132e57ffd24948e17af7a4b54a54303b4590"},{"sha":"168cfe4dbf1e6413ae4328970676ff1d519e018b","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: 7660/1: tlb: add branch predictor maintenance operations\n\nThe ARM architecture requires explicit branch predictor maintenance\nwhen updating an instruction stream for a given virtual address. In\nreality, this isn't so much of a burden because the branch predictor\nis flushed during the cache maintenance required to make the new\ninstructions visible to the I-side of the processor.\n\nHowever, there are still some cases where explicit flushing is required,\nso add a local_bp_flush_all operation to deal with this.\n\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/168cfe4dbf1e6413ae4328970676ff1d519e018b"},{"sha":"c97ec923b2503684fe5cf78afed3b34841af30db","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: 7445/1: mm: update CONTEXTIDR register to contain PID of current process\n\nThis patch introduces a new Kconfig option which, when enabled, causes\nthe kernel to write the PID of the current task into the PROCID field\nof the CONTEXTIDR on context switch. This is useful when analysing\nhardware trace, since writes to this register can be configured to emit\nan event into the trace stream.\n\nThe thread notifier for writing the PID is deliberately kept separate\nfrom the ASID-writing code so that we can support newer processors using\nLPAE, where the ASID is stored in TTBR0. As such, the switch_mm code is\nupdated to perform a read-modify-write sequence to ensure that we don't\nclobber the PID on CPUs using the classic 2-level page tables.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/c97ec923b2503684fe5cf78afed3b34841af30db"},{"sha":"a4231c9b4e1745606b7a8a227660fa047a91b611","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: 7502/1: contextidr: avoid using bfi instruction during notifier\n\nThe bfi instruction is not available on ARMv6, so instead use an and/orr\nsequence in the contextidr_notifier. This gets rid of the assembler\nerror:\n\n  Assembler messages:\n  Error: selected processor does not support ARM mode `bfi r3,r2,#0,#8'\n\nReported-by: Arnd Bergmann <arnd@arndb.de>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/a4231c9b4e1745606b7a8a227660fa047a91b611"},{"sha":"c7db9a9d8046d5e87992aecfe732502183f7ce8c","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: mm: remove IPI broadcasting on ASID rollover\n\nASIDs are allocated to MMU contexts based on a rolling counter. This\nmeans that after 255 allocations we must invalidate all existing ASIDs\nvia an expensive IPI mechanism to synchronise all of the online CPUs and\nensure that all tasks execute with an ASID from the new generation.\n\nThis patch changes the rollover behaviour so that we rely instead on the\nhardware broadcasting of the TLB invalidation to avoid the IPI calls.\nThis works by keeping track of the active ASID on each core, which is\nthen reserved in the case of a rollover so that currently scheduled\ntasks can continue to run. For cores without hardware TLB broadcasting,\nwe keep track of pending flushes in a cpumask, so cores can flush their\nlocal TLB before scheduling a new mm.\n\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nTested-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/c7db9a9d8046d5e87992aecfe732502183f7ce8c"},{"sha":"54ab89314a067f487d20bdcd0e4a7659c2392a07","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: mm: avoid taking ASID spinlock on fastpath\n\nWhen scheduling a new mm, we take a spinlock so that we can:\n\n  1. Safely allocate a new ASID, if required\n  2. Update our active_asids field without worrying about parallel\n     updates to reserved_asids\n  3. Ensure that we flush our local TLB, if required\n\nHowever, this has the nasty affect of serialising context-switch across\nall CPUs in the system. The usual (fast) case is where the next mm has\na valid ASID for the current generation. In such a scenario, we can\navoid taking the lock and instead use atomic64_xchg to update the\nactive_asids variable for the current CPU. If a rollover occurs on\nanother CPU (which would take the lock), when copying the active_asids\ninto the reserved_asids another atomic64_xchg is used to replace each\nactive_asids with 0. The fast path can then detect this case and fall\nback to spinning on the lock.\n\nTested-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/54ab89314a067f487d20bdcd0e4a7659c2392a07"},{"sha":"039d47d96c085039d735565a74712f5d5dd375f4","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: mm: use bitmap operations when allocating new ASIDs\n\nWhen allocating a new ASID, we must take care not to re-assign a\nreserved ASID-value to a new mm. This requires us to check each\ncandidate ASID against those currently reserved by other cores before\nassigning a new ASID to the current mm.\n\nThis patch improves the ASID allocation algorithm by using a\nbitmap-based approach. Rather than iterating over the reserved ASID\narray for each candidate ASID, we simply find the first zero bit,\nensuring that those indices corresponding to reserved ASIDs are set\nwhen flushing during a rollover event.\n\nTested-by: Marc Zyngier <marc.zyngier@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/039d47d96c085039d735565a74712f5d5dd375f4"},{"sha":"218bd80dae32204676757668e218d4b6c79fa482","author":{"name":"Nicolas Pitre","email":"821418b0a29e813296bdaa58f6aecc4445fd1b69@linaro.org"},"message":"ARM: 7582/2: rename kvm_seq to vmalloc_seq so to avoid confusion with KVM\n\nThe kvm_seq value has nothing to do what so ever with this other KVM.\nGiven that KVM support on ARM is imminent, it's best to rename kvm_seq\ninto something else to clearly identify what it is about i.e. a sequence\nnumber for vmalloc section mappings.\n\nSigned-off-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/218bd80dae32204676757668e218d4b6c79fa482"},{"sha":"9de102eaca88f5115c731aba3a57fee09f26e60e","author":{"name":"Ben Dooks","email":"f0709c3071c030bf687deb337699eaa57aa0836e@fluff.org"},"message":"ARM: 7649/1: mm: mm->context.id fix for big-endian\n\nSince the new ASID code in b5466f8728527a05a493cc4abe9e6f034a1bbaab\n(\"ARM: mm: remove IPI broadcasting on ASID rollover\") was changed to\nuse 64bit operations it has broken the BE operation due to an issue\nwith the MM code accessing sub-fields of mm->context.id.\n\nWhen running in BE mode we see the values in mm->context.id are stored\nwith the highest value first, so the LDR in the arch/arm/mm/proc-macros.S\nreads the wrong part of this field. To resolve this, change the LDR in\nthe mmid macro to load from +4.\n\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Ben Dooks <ben.dooks@codethink.co.uk>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/9de102eaca88f5115c731aba3a57fee09f26e60e"},{"sha":"e606c6d78757b7a3579316d877f32e8d5a9570b8","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: 7658/1: mm: fix race updating mm->context.id on ASID rollover\n\nIf a thread triggers an ASID rollover, other threads of the same process\nmust be made to wait until the mm->context.id for the shared mm_struct\nhas been updated to new generation and associated book-keeping (e.g.\nTLB invalidation) has ben performed.\n\nHowever, there is a *tiny* window where both mm->context.id and the\nrelevant active_asids entry are updated to the new generation, but the\nTLB flush has not been performed, which could allow another thread to\nreturn to userspace with a dirty TLB, potentially leading to data\ncorruption. In reality this will never occur because one CPU would need\nto perform a context-switch in the time it takes another to do a couple\nof atomic test/set operations but we should plug the race anyway.\n\nThis patch moves the active_asids update until after the potential TLB\nflush on context-switch.\n\nCc: <stable@vger.kernel.org> # 3.8\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/e606c6d78757b7a3579316d877f32e8d5a9570b8"},{"sha":"8ea8f795cd4a0c4c7e2045f9a9c0f2eb401525f0","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: 7659/1: mm: make mm->context.id an atomic64_t variable\n\nmm->context.id is updated under asid_lock when a new ASID is allocated\nto an mm_struct. However, it is also read without the lock when a task\nis being scheduled and checking whether or not the current ASID\ngeneration is up-to-date.\n\nIf two threads of the same process are being scheduled in parallel and\nthe bottom bits of the generation in their mm->context.id match the\ncurrent generation (that is, the mm_struct has not been used for ~2^24\nrollovers) then the non-atomic, lockless access to mm->context.id may\nyield the incorrect ASID.\n\nThis patch fixes this issue by making mm->context.id and atomic64_t,\nensuring that the generation is always read consistently. For code that\nonly requires access to the ASID bits (e.g. TLB flushing by mm), then\nthe value is accessed directly, which GCC converts to an ldrb.\n\nCc: <stable@vger.kernel.org> # 3.8\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/8ea8f795cd4a0c4c7e2045f9a9c0f2eb401525f0"},{"sha":"0e4c2ce25b80530445d5b363486070803097a5e5","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: 7661/1: mm: perform explicit branch predictor maintenance when required\n\nThe ARM ARM requires branch predictor maintenance if, for a given ASID,\nthe instructions at a specific virtual address appear to change.\n\nFrom the kernel's point of view, that means:\n\n\t- Changing the kernel's view of memory (e.g. switching to the\n\t  identity map)\n\t- ASID rollover (since ASIDs will be re-allocated to new tasks)\n\nThis patch adds explicit branch predictor maintenance when either of the\ntwo conditions above are met.\n\nReviewed-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/0e4c2ce25b80530445d5b363486070803097a5e5"},{"sha":"f10bd984bea4fc0266b989061b2a3bd359d78ff3","author":{"name":"Catalin Marinas","email":"6aa257b0f6444d48b36b727fdf3f5c1074b85fd0@arm.com"},"message":"ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)\n\nOn Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down\nall use of the old entries. This patch implements the erratum workaround\nwhich consists of:\n\n1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.\n2. Send IPI to the CPUs that are running the same mm (and ASID) as the\n   one being invalidated (or all the online CPUs for global pages).\n3. CPU receiving the IPI executes a DMB and CLREX (part of the exception\n   return code already).\n\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\nSigned-off-by: Vidir Alexander Jonsson <valex@valex.is>\n\nConflicts:\n\tarch/arm/Kconfig","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/f10bd984bea4fc0266b989061b2a3bd359d78ff3"},{"sha":"95e26fa13b704aa53a0c66738ff9560851c5756d","author":{"name":"Viresh Kumar","email":"4ca49bc1dcfdfc376d29da1eb07a3e0b3cd46daa@linaro.org"},"message":"ARM: mm: uninitialized warning corrections\n\nThe variables here are really not used uninitialized.\n\narch/arm/mm/alignment.c: In function 'do_alignment':\narch/arm/mm/alignment.c:327:15: warning: 'offset.un' may be used uninitialized in this function [-Wmaybe-uninitialized]\narch/arm/mm/alignment.c:748:21: note: 'offset.un' was declared here\n\nSigned-off-by: Viresh Kumar <viresh.kumar@linaro.org>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/95e26fa13b704aa53a0c66738ff9560851c5756d"},{"sha":"c04d5a023c74a29279d8dd9dd633b37158b903dc","author":{"name":"Russell King","email":"8640768d851c67eb4c0e8bfcf2aabcc8010b9372@arm.linux.org.uk"},"message":"ARM: fix warnings about atomic64_read\n\nFix:\nnet/netfilter/xt_connbytes.c: In function 'connbytes_mt':\nnet/netfilter/xt_connbytes.c:43: warning: passing argument 1 of 'atomic64_read' discards qualifiers from pointer target type\n...\n\nby adding the missing const.\n\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/c04d5a023c74a29279d8dd9dd633b37158b903dc"},{"sha":"52249d496931cf604eb3d2631d8ad94a934f0ec8","author":{"name":"Lorenzo Pieralisi","email":"4d7b4dbe898a2b7e1890a3f7add8330fb0f08d60@arm.com"},"message":"ARM: mm: define LoUIS API for cache maintenance ops\n\nARM v7 architecture introduced the concept of cache levels and related\ncoherency requirements. New processors like A7 and A15 embed an\nL2 unified cache controller that becomes part of the cache level\nhierarchy. Some operations in the kernel like cpu_suspend and __cpu_disable\ndoes not require a flush of the entire cache hierarchy to DRAM but just the\ncache levels belonging to the Level of Unification Inner Shareable (LoUIS),\nwhich in most of ARM v7 systems correspond to L1.\n\nThe current cache flushing API used in cpu_suspend and __cpu_disable,\nflush_cache_all(), ends up flushing the whole cache hierarchy since for\nv7 it cleans and invalidates all cache levels up to Level of Coherency\n(LoC) which cripples system performance when used in hot paths like hotplug\nand cpuidle.\n\nTherefore a new kernel cache maintenance API must be added to the\ncpu_cache_fns structure of pointers to cope with latest ARM system requirements.\nThis patch adds flush_cache_louis() to the ARM kernel cache maintenance API.\n\nThis function cleans and invalidates all data cache levels up to the\nlevel of unification inner shareable (LoUIS) and invalidates the instruction\ncache.\n\nThe cpu_cache_fns struct reflects this change by adding a new function pointer\nthat is initialized by arch specific assembly files.\n\nBy default, all existing ARM archs do not instantiate any cache LoUIS function\npointer, and flush_dcache_louis just falls back to flush_kern_all.\n\nReviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>\nSigned-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>","distinct":true,"url":"https://api.github.com/repos/sigma-1/kernel/commits/52249d496931cf604eb3d2631d8ad94a934f0ec8"}]}
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