{"action":"created","comment":{"url":"https://api.github.com/repos/OP-TEE/optee_os/pulls/comments/71476142","id":71476142,"diff_hunk":"@@ -0,0 +1,366 @@\n+/*\n+ * Copyright (c) 2016, Xilinx Inc.\n+ * All rights reserved.\n+ *\n+ * Redistribution and use in source and binary forms, with or without\n+ * modification, are permitted provided that the following conditions are met:\n+ *\n+ * 1. Redistributions of source code must retain the above copyright notice,\n+ * this list of conditions and the following disclaimer.\n+ *\n+ * 2. Redistributions in binary form must reproduce the above copyright notice,\n+ * this list of conditions and the following disclaimer in the documentation\n+ * and/or other materials provided with the distribution.\n+ *\n+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\n+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\n+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n+ * POSSIBILITY OF SUCH DAMAGE.\n+ */\n+\n+#include <io.h>\n+#include <kernel/static_ta.h>\n+#include <kernel/tz_ssvce.h>\n+#include <mm/core_memprot.h>\n+#include <tee_internal_api.h>\n+#include <tee_internal_api_extensions.h>\n+#include <util.h>\n+#include <zynqmp_bsload.h>\n+#include \"platform_config.h\"\n+\n+#define TA_NAME \"BSLOAD\"\n+\n+#define STR_TRACE_USER_TA TA_NAME\n+\n+static vaddr_t csu_base;\n+static vaddr_t csudma_base;\n+\n+#define CSU_PA_BASE\t\t\tCSU_BASE\n+#define CSUDMA_PA_BASE\t\t\tCSUDMA_BASE\n+\n+#define CSU_SSS_CONFIG\t\t\t(csu_base + 0x08)\n+#define CSU_SSS_CFG_PCAP_SSS_MASK\t0xF\n+#define CSU_SSS_CFG_PCAP_SSS_SHFT\t0x0\n+#define CSU_SSS_CFG_PCAP_DMA_DATA\t0x5\n+#define CSU_PCAP_RESET\t\t\t(csu_base + 0x300C)\n+#define CSU_PCAP_RDWR\t\t\t(csu_base + 0x3004)\n+#define CSU_PCAP_CTRL\t\t\t(csu_base + 0x3008)\n+#define CSU_PCAP_PROG\t\t\t(csu_base + 0x3000)\n+#define CSU_PCAP_STATUS\t\t\t(csu_base + 0x3010)\n+#define CSU_PCAP_RESET_RESET\t\tBIT(0)\n+#define CSU_PCAP_CTRL_PCAP_PR\t\tBIT(0)\n+#define CSU_PCAP_PROG_PCFG_PROG_B\tBIT(0)\n+#define CSU_PCAP_STATUS_PCAP_WR_IDLE\tBIT(0)\n+#define CSU_PCAP_STATUS_PL_INIT\t\tBIT(2)\n+#define CSU_PCAP_STATUS_PL_DONE\t\tBIT(3)\n+#define CSU_PCAP_STATUS_PL_RESET_B\tBIT(6)\n+\n+#define CSUDMA_SRC_ADDR\t\t\t(csudma_base + 0x000)\n+#define CSUDMA_SRC_CRC\t\t\t(csudma_base + 0x010)\n+#define CSUDMA_SRC_SIZE\t\t\t(csudma_base + 0x004)\n+#define CSUDMA_SRC_I_STS\t\t(csudma_base + 0x014)\n+#define CSUDMA_SRC_ADDR_MSB\t\t(csudma_base + 0x028)\n+#define CSUDMA_SRC_I_STS_DONE\t\tBIT(1)\n+#define CSUDMA_SRC_SIZE_MASK\t\t0x1ffffffc\n+\n+#define DUMMY_WORD\t\t\t0xffffffff\n+#define BS_SIZE_MAX\t\t\t0x1fffffff\n+\n+/* Xilinx binary format header */\n+static const uint32_t bin_format[] = {\n+\tDUMMY_WORD, /* Dummy words */\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\t0x000000bb, /* Sync word */\n+\t0x11220044, /* Sync word */\n+\tDUMMY_WORD,\n+\tDUMMY_WORD,\n+\t0xaa995566, /* Sync word */\n+};\n+\n+static TEE_Result poll_reg_tout_32(vaddr_t addr, uint32_t mask, uint32_t val,\n+\t\t\t\t   ssize_t tout)\n+{\n+\tuint32_t reg;\n+\n+\tdo {\n+\t\treg = read32(addr);\n+\t} while (((reg & mask) != val) && tout--);\n+\n+\tif (tout <= 0)\n+\t\treturn TEE_ERROR_GENERIC;\n+\n+\treturn TEE_SUCCESS;\n+}\n+\n+static TEE_Result check_header(const paddr_t buf)\n+{\n+\tconst uint32_t *test = (const uint32_t *)buf;\n+\n+\tfor (size_t i = 0; i < ARRAY_SIZE(bin_format); i++) {\n+\t\tif (test[i] != bin_format[i])\n+\t\t\treturn TEE_ERROR_BAD_FORMAT;\n+\t}\n+\n+\treturn TEE_SUCCESS;\n+}\n+\n+static TEE_Result pcap_init(void)\n+{\n+\tTEE_Result ret;\n+\n+\t/* reset PCAP */\n+\twrite32(CSU_PCAP_RESET_RESET, CSU_PCAP_RESET);\n+\twrite32(0, CSU_PCAP_RESET);\n+\n+\twrite32(CSU_PCAP_CTRL_PCAP_PR, CSU_PCAP_CTRL);\n+\twrite32(0, CSU_PCAP_RDWR);\n+\n+\t/* reset PL */\n+\twrite32(0, CSU_PCAP_PROG);\n+\tret = poll_reg_tout_32(CSU_PCAP_STATUS, CSU_PCAP_STATUS_PL_RESET_B, 0,\n+\t\t\t       0x8000000);\n+\tif (ret != TEE_SUCCESS) {\n+\t\tDMSG(\"timeout waiting for PL reset\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\twrite32(CSU_PCAP_PROG_PCFG_PROG_B, CSU_PCAP_PROG);\n+\tret = poll_reg_tout_32(CSU_PCAP_STATUS, CSU_PCAP_STATUS_PL_INIT,\n+\t\t\t       CSU_PCAP_STATUS_PL_INIT, 0x8000000);\n+\tif (ret != TEE_SUCCESS) {\n+\t\tDMSG(\"timeout waiting for PL init done\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn TEE_SUCCESS;\n+}\n+\n+static TEE_Result pcap_write(uint64_t srcaddr, uint32_t size)\n+{\n+\tTEE_Result ret;\n+\tuint32_t regval;\n+\n+\twrite32(0, CSUDMA_SRC_CRC);\n+\n+\tregval = read32(CSU_SSS_CONFIG);\n+\tregval &= CSU_SSS_CFG_PCAP_SSS_MASK;\n+\tregval |= (CSU_SSS_CFG_PCAP_DMA_DATA << CSU_SSS_CFG_PCAP_SSS_SHFT);\n+\twrite32(regval, CSU_SSS_CONFIG);\n+\n+\twrite32((uint32_t)srcaddr, CSUDMA_SRC_ADDR);\n+\twrite32((srcaddr >> 32) & 0x1FFFF, CSUDMA_SRC_ADDR_MSB);\n+\twrite32(size & CSUDMA_SRC_SIZE_MASK, CSUDMA_SRC_SIZE);\n+\n+\tret = poll_reg_tout_32(CSUDMA_SRC_I_STS, CSUDMA_SRC_I_STS_DONE,\n+\t\t\t       CSUDMA_SRC_I_STS_DONE, 0x8000000);\n+\tif (ret != TEE_SUCCESS) {\n+\t\tDMSG(\"timeout writing bitstream\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\twrite32(CSUDMA_SRC_I_STS_DONE, CSUDMA_SRC_I_STS);\n+\n+\tret = poll_reg_tout_32(CSU_PCAP_STATUS, CSU_PCAP_STATUS_PCAP_WR_IDLE,\n+\t\t\t       CSU_PCAP_STATUS_PCAP_WR_IDLE, 0x8000000);\n+\tif (ret != TEE_SUCCESS) {\n+\t\tDMSG(\"timeout waiting for CSUDMA idle\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tDMSG(\"SRC_CRC: %#x\\n\", read32(CSUDMA_SRC_CRC));\n+\n+\treturn TEE_SUCCESS;\n+}\n+\n+static TEE_Result wait_done(void)\n+{\n+\tTEE_Result ret;\n+\tuint32_t regval;\n+\n+\tret = poll_reg_tout_32(CSU_PCAP_STATUS, CSU_PCAP_STATUS_PL_DONE,\n+\t\t\t       CSU_PCAP_STATUS_PL_DONE, 0x8000000);\n+\tif (ret != TEE_SUCCESS) {\n+\t\tDMSG(\"timeout waiting for PL done\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tregval = read32(CSU_PCAP_RESET);\n+\tregval |= CSU_PCAP_RESET_RESET;\n+\twrite32(regval, CSU_PCAP_RESET);\n+\tret = poll_reg_tout_32(CSU_PCAP_RESET, CSU_PCAP_RESET_RESET,\n+\t\t\t       CSU_PCAP_RESET_RESET, 0x8000000);\n+\tif (ret != TEE_SUCCESS) {\n+\t\tDMSG(\"timeout waiting for PCAP reset assert\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn TEE_SUCCESS;\n+}\n+\n+static TEE_Result do_load_bs(vaddr_t bs, size_t sz, uint64_t flags)\n+{\n+\tpaddr_t addr;\n+\tTEE_Result ret;\n+\t(void)flags;\n+\n+\t/* sanity check bitstream */\n+\tif (bs & 0x3)\n+\t\treturn TEE_ERROR_BAD_PARAMETERS;\n+\n+\tif (sz > BS_SIZE_MAX)\n+\t\treturn TEE_ERROR_EXCESS_DATA;\n+\n+\tret = check_header(bs);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\taddr = virt_to_phys((void *)bs);\n+\tif (!addr) {\n+\t\tDMSG(\"no mapping found for va '%#lx'\\n\", bs);\n+\t\treturn TEE_ERROR_GENERIC;\n+\t}\n+\tDMSG(\"bitstream va:%#lx, pa:%#lx, sz:%#zx\\n\", bs, addr, sz);\n+\n+\tflush_dcache_range(bs, sz);","path":"core/arch/arm/plat-zynqmp/sta_bsload.c","position":245,"original_position":245,"commit_id":"d789d0cf45a1ec8285a671b7db5fc88ee368ed0c","original_commit_id":"d789d0cf45a1ec8285a671b7db5fc88ee368ed0c","user":{"login":"jenswi-linaro","id":6150306,"avatar_url":"https://avatars.githubusercontent.com/u/6150306?v=3","gravatar_id":"","url":"https://api.github.com/users/jenswi-linaro","html_url":"https://github.com/jenswi-linaro","followers_url":"https://api.github.com/users/jenswi-linaro/followers","following_url":"https://api.github.com/users/jenswi-linaro/following{/other_user}","gists_url":"https://api.github.com/users/jenswi-linaro/gists{/gist_id}","starred_url":"https://api.github.com/users/jenswi-linaro/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jenswi-linaro/subscriptions","organizations_url":"https://api.github.com/users/jenswi-linaro/orgs","repos_url":"https://api.github.com/users/jenswi-linaro/repos","events_url":"https://api.github.com/users/jenswi-linaro/events{/privacy}","received_events_url":"https://api.github.com/users/jenswi-linaro/received_events","type":"User","site_admin":false},"body":"Please use `cache_maintenance_l1(DCACHE_AREA_CLEAN_INV, (void *)bs, sz)` instead.","created_at":"2016-07-20T07:19:44Z","updated_at":"2016-07-20T07:19:44Z","html_url":"https://github.com/OP-TEE/optee_os/pull/928#discussion_r71476142","pull_request_url":"https://api.github.com/repos/OP-TEE/optee_os/pulls/928","_links":{"self":{"href":"https://api.github.com/repos/OP-TEE/optee_os/pulls/comments/71476142"},"html":{"href":"https://github.com/OP-TEE/optee_os/pull/928#discussion_r71476142"},"pull_request":{"href":"https://api.github.com/repos/OP-TEE/optee_os/pulls/928"}}},"pull_request":{"url":"https://api.github.com/repos/OP-TEE/optee_os/pulls/928","id":78081602,"html_url":"https://github.com/OP-TEE/optee_os/pull/928","diff_url":"https://github.com/OP-TEE/optee_os/pull/928.diff","patch_url":"https://github.com/OP-TEE/optee_os/pull/928.patch","issue_url":"https://api.github.com/repos/OP-TEE/optee_os/issues/928","number":928,"state":"open","locked":false,"title":"[RFC] zynqmp: Add static TA for bitstream loading","user":{"login":"sorenb-xlnx","id":3967646,"avatar_url":"https://avatars.githubusercontent.com/u/3967646?v=3","gravatar_id":"","url":"https://api.github.com/users/sorenb-xlnx","html_url":"https://github.com/sorenb-xlnx","followers_url":"https://api.github.com/users/sorenb-xlnx/followers","following_url":"https://api.github.com/users/sorenb-xlnx/following{/other_user}","gists_url":"https://api.github.com/users/sorenb-xlnx/gists{/gist_id}","starred_url":"https://api.github.com/users/sorenb-xlnx/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sorenb-xlnx/subscriptions","organizations_url":"https://api.github.com/users/sorenb-xlnx/orgs","repos_url":"https://api.github.com/users/sorenb-xlnx/repos","events_url":"https://api.github.com/users/sorenb-xlnx/events{/privacy}","received_events_url":"https://api.github.com/users/sorenb-xlnx/received_events","type":"User","site_admin":false},"body":"I created this patch for a proof of concept for loading a bitstream into the FPGA on ZynqMP devices through an OP-TEE TA (the HW for programming a bitstream allows secure accessses only).\r\nCurrently I'm just looking for general feedback on the overall solution. Though, I'd be inclined to go for a merge if feedback is positive.\r\nThe user-space portion is available in https://github.com/sorenb-xlnx/optee_bsload.\r\n\r\nThe high level flow is:\r\n- userspace opens a bitstream (using mmap) and provides address and size as temp memref to OP-TEE (a second argument is used to pass flags, but so far none are implemented. But in the future cases like chunked or partial configuration may require some flags)\r\n- the TA programs the HW to load the bitstream into the FPGA","created_at":"2016-07-20T02:59:07Z","updated_at":"2016-07-20T07:19:44Z","closed_at":null,"merged_at":null,"merge_commit_sha":"3ceffe8e2975d770b80afde3bc2e3c2d87a1d39a","assignee":null,"assignees":[],"milestone":null,"commits_url":"https://api.github.com/repos/OP-TEE/optee_os/pulls/928/commits","review_comments_url":"https://api.github.com/repos/OP-TEE/optee_os/pulls/928/comments","review_comment_url":"https://api.github.com/repos/OP-TEE/optee_os/pulls/comments{/number}","comments_url":"https://api.github.com/repos/OP-TEE/optee_os/issues/928/comments","statuses_url":"https://api.github.com/repos/OP-TEE/optee_os/statuses/d789d0cf45a1ec8285a671b7db5fc88ee368ed0c","head":{"label":"sorenb-xlnx:bsload","ref":"bsload","sha":"d789d0cf45a1ec8285a671b7db5fc88ee368ed0c","user":{"login":"sorenb-xlnx","id":3967646,"avatar_url":"https://avatars.githubusercontent.com/u/3967646?v=3","gravatar_id":"","url":"https://api.github.com/users/sorenb-xlnx","html_url":"https://github.com/sorenb-xlnx","followers_url":"https://api.github.com/users/sorenb-xlnx/followers","following_url":"https://api.github.com/users/sorenb-xlnx/following{/other_user}","gists_url":"https://api.github.com/users/sorenb-xlnx/gists{/gist_id}","starred_url":"https://api.github.com/users/sorenb-xlnx/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sorenb-xlnx/subscriptions","organizations_url":"https://api.github.com/users/sorenb-xlnx/orgs","repos_url":"https://api.github.com/users/sorenb-xlnx/repos","events_url":"https://api.github.com/users/sorenb-xlnx/events{/privacy}","received_events_url":"https://api.github.com/users/sorenb-xlnx/received_events","type":"User","site_admin":false},"repo":{"id":59906116,"name":"optee_os","full_name":"sorenb-xlnx/optee_os","owner":{"login":"sorenb-xlnx","id":3967646,"avatar_url":"https://avatars.githubusercontent.com/u/3967646?v=3","gravatar_id":"","url":"https://api.github.com/users/sorenb-xlnx","html_url":"https://github.com/sorenb-xlnx","followers_url":"https://api.github.com/users/sorenb-xlnx/followers","following_url":"https://api.github.com/users/sorenb-xlnx/following{/other_user}","gists_url":"https://api.github.com/users/sorenb-xlnx/gists{/gist_id}","starred_url":"https://api.github.com/users/sorenb-xlnx/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sorenb-xlnx/subscriptions","organizations_url":"https://api.github.com/users/sorenb-xlnx/orgs","repos_url":"https://api.github.com/users/sorenb-xlnx/repos","events_url":"https://api.github.com/users/sorenb-xlnx/events{/privacy}","received_events_url":"https://api.github.com/users/sorenb-xlnx/received_events","type":"User","site_admin":false},"private":false,"html_url":"https://github.com/sorenb-xlnx/optee_os","description":"Trusted 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