{"push_id":1155194798,"size":3,"distinct_size":3,"ref":"refs/heads/jasper_devel","head":"41b47ed4e30483b4060faec1b88180bc081898d2","before":"f0aa5ff81e587ddec95d9147cb4349b9f12f73ca","commits":[{"sha":"a2426656ee2c1dfaa9eab255caf8d294c4a79787","author":{"name":"Jack Hickish","email":"16453375fe9012135e1dcf222702b8dffc201ce9@acme1.digilab.pvt"},"message":"Replace PCORE yellow block with IP yellow block.\n\nIP yellow block adds an IP core, generated by a separate\nsysgen compile, for blackboxing.\n\nIt might be worth usign this code to add the \"main\" sysgen\ndesign to vivado, rather than the current system of\nadding all the source files from an hdl netlist.","distinct":true,"url":"https://api.github.com/repos/jack-h/mlib_devel/commits/a2426656ee2c1dfaa9eab255caf8d294c4a79787"},{"sha":"6248f6409256955e97f1861ad78df5e7fe83514a","author":{"name":"Jack Hickish","email":"16453375fe9012135e1dcf222702b8dffc201ce9@acme1.digilab.pvt"},"message":"Add sw reg and shared bram entries to forwarding table\n\nSo \"software register\" and \"Shared BRAM\" get updated with\n\"software_register\" and \"Shared_BRAM\" blocks from the library,\nrespectively.","distinct":true,"url":"https://api.github.com/repos/jack-h/mlib_devel/commits/6248f6409256955e97f1861ad78df5e7fe83514a"},{"sha":"41b47ed4e30483b4060faec1b88180bc081898d2","author":{"name":"Jack Hickish","email":"16453375fe9012135e1dcf222702b8dffc201ce9@acme1.digilab.pvt"},"message":"Fix constrain generation for vector signals\n\nSome mixup between symbolic indices and signal indices.","distinct":true,"url":"https://api.github.com/repos/jack-h/mlib_devel/commits/41b47ed4e30483b4060faec1b88180bc081898d2"}]}
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