{"push_id":1325801091,"size":6,"distinct_size":6,"ref":"refs/heads/amlogic/v4.8/gpioirq","head":"16f0908c453d370fee35557d4674cb4a93e0dd81","before":"1d8612f683901438c4c4c43f71a16da0a48ad6a8","commits":[{"sha":"ff1ccb676f08bd6dc0cfd0fcb91c3e73ac492fa2","author":{"name":"Jerome Brunet","email":"61fc130920b45616041d66e7665f550b55d505a5@baylibre.com"},"message":"irqchip: meson: add support for gpio interrupt controller\n\nAdd support for the intterupt gpio controller found on Amlogic's meson\nSoC family.\n\nUnlike what the IP name suggest, it is not directly linked to the gpio\nsubsystem. It is actually an indepedent IP that is able to spy on the\nSoC pad. For that purpose, it can mux and filter (edge or level and\npolarity) any single SoC pad to one of the 8 GIC's interrupts it owns.\n\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>","distinct":true,"url":"https://api.github.com/repos/jeromebrunet/linux/commits/ff1ccb676f08bd6dc0cfd0fcb91c3e73ac492fa2"},{"sha":"c676252562b4e016dacefce85aaaba4d0260881a","author":{"name":"Jerome Brunet","email":"61fc130920b45616041d66e7665f550b55d505a5@baylibre.com"},"message":"pinctrl: meson: update pinctrl data with gpio irq base number\n\nThis patch extends meson's pinctrl SoC specific data by adding the gpio irq\nbase number. This will allow gpios to request an interrupt on the gpio\ninterrupt controller using this base irq number the pin offset in bank\n\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>","distinct":true,"url":"https://api.github.com/repos/jeromebrunet/linux/commits/c676252562b4e016dacefce85aaaba4d0260881a"},{"sha":"68a01ada6b3a2bd9619ff0ebd19e380edfc095d3","author":{"name":"Jerome Brunet","email":"61fc130920b45616041d66e7665f550b55d505a5@baylibre.com"},"message":"pinctrl: meson: allow gpio to request irq\n\nAdd the ability for gpio to request irq from the gpio interrupt controller if\npresent. We have to specificaly that the parent interrupt controller is the\ngpio interrupt controller because gpio on meson SoCs can't generate interrupt\ndirectly on the GIC.\n\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>","distinct":true,"url":"https://api.github.com/repos/jeromebrunet/linux/commits/68a01ada6b3a2bd9619ff0ebd19e380edfc095d3"},{"sha":"21ca1450852a9fc65e6ce6dfa0f0a8e153ed48ce","author":{"name":"Jerome Brunet","email":"61fc130920b45616041d66e7665f550b55d505a5@baylibre.com"},"message":"ARM64: meson: enable MESON_IRQ_GPIO in Kconfig\n\nAdd select MESON_IRQ_GPIO in Kconfig for Amlogic's Meson SoC family\n\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>","distinct":true,"url":"https://api.github.com/repos/jeromebrunet/linux/commits/21ca1450852a9fc65e6ce6dfa0f0a8e153ed48ce"},{"sha":"37ff489e630c045fc6bb5128631667cfeeb12f52","author":{"name":"Jerome Brunet","email":"61fc130920b45616041d66e7665f550b55d505a5@baylibre.com"},"message":"ARM64: dts: amlogic: enable gpio interrupt controller on gxbb\n\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>","distinct":true,"url":"https://api.github.com/repos/jeromebrunet/linux/commits/37ff489e630c045fc6bb5128631667cfeeb12f52"},{"sha":"16f0908c453d370fee35557d4674cb4a93e0dd81","author":{"name":"Jerome Brunet","email":"61fc130920b45616041d66e7665f550b55d505a5@baylibre.com"},"message":"ARM: dts: amlogic: enable gpio interrupt controller on meson8b\n\nSigned-off-by: Jerome Brunet <jbrunet@baylibre.com>","distinct":true,"url":"https://api.github.com/repos/jeromebrunet/linux/commits/16f0908c453d370fee35557d4674cb4a93e0dd81"}]}
{"actor":{"display_login":"jeromebrunet"}}