{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/firrtl/issues/294","repository_url":"https://api.github.com/repos/ucb-bar/firrtl","labels_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/294/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/294/comments","events_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/294/events","html_url":"https://github.com/ucb-bar/firrtl/pull/294","id":176163690,"number":294,"title":"Bug fix -- remove all empty expressions after ReplSeqMem passes","user":{"login":"shunshou","id":6607638,"avatar_url":"https://avatars.githubusercontent.com/u/6607638?v=3","gravatar_id":"","url":"https://api.github.com/users/shunshou","html_url":"https://github.com/shunshou","followers_url":"https://api.github.com/users/shunshou/followers","following_url":"https://api.github.com/users/shunshou/following{/other_user}","gists_url":"https://api.github.com/users/shunshou/gists{/gist_id}","starred_url":"https://api.github.com/users/shunshou/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/shunshou/subscriptions","organizations_url":"https://api.github.com/users/shunshou/orgs","repos_url":"https://api.github.com/users/shunshou/repos","events_url":"https://api.github.com/users/shunshou/events{/privacy}","received_events_url":"https://api.github.com/users/shunshou/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":11,"created_at":"2016-09-10T06:57:22Z","updated_at":"2016-09-11T05:19:59Z","closed_at":null,"pull_request":{"url":"https://api.github.com/repos/ucb-bar/firrtl/pulls/294","html_url":"https://github.com/ucb-bar/firrtl/pull/294","diff_url":"https://github.com/ucb-bar/firrtl/pull/294.diff","patch_url":"https://github.com/ucb-bar/firrtl/pull/294.patch"},"body":"Addresses #292 \r\n@ccelio can you try this and see if it works  (compiles + simulates)?\r\n@jackkoenig @azidar -- do you think it's better to do something like this or just case out WSubField, WSubIndex, and EmptyExpression (assuming those are the only 3 possible?) \r\n\r\n"},"comment":{"url":"https://api.github.com/repos/ucb-bar/firrtl/issues/comments/246162601","html_url":"https://github.com/ucb-bar/firrtl/pull/294#issuecomment-246162601","issue_url":"https://api.github.com/repos/ucb-bar/firrtl/issues/294","id":246162601,"user":{"login":"shunshou","id":6607638,"avatar_url":"https://avatars.githubusercontent.com/u/6607638?v=3","gravatar_id":"","url":"https://api.github.com/users/shunshou","html_url":"https://github.com/shunshou","followers_url":"https://api.github.com/users/shunshou/followers","following_url":"https://api.github.com/users/shunshou/following{/other_user}","gists_url":"https://api.github.com/users/shunshou/gists{/gist_id}","starred_url":"https://api.github.com/users/shunshou/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/shunshou/subscriptions","organizations_url":"https://api.github.com/users/shunshou/orgs","repos_url":"https://api.github.com/users/shunshou/repos","events_url":"https://api.github.com/users/shunshou/events{/privacy}","received_events_url":"https://api.github.com/users/shunshou/received_events","type":"User","site_admin":false},"created_at":"2016-09-11T05:19:59Z","updated_at":"2016-09-11T05:19:59Z","body":"Any suggestions on how to handle unbounded datatypes or imposing some looser restrictions? \r\n\r\nThat's why Chisel3 limits wmasks to Vecs as the top level aggregates, but it's just slightly weird that FIRRTL doesn't follow the same rules.\r\n\r\nWell, courtesy of Albert's Utils, my current black boxing pass does something like:\r\n\r\n[Concatenates bundle elements and properly handles at least Bundles of ground types, except the conf file is wrong...]\r\n\r\n```\r\nmodule entries_info2(\r\n  input  [4:0] R0_addr,\r\n  input   R0_en,\r\n  input   R0_clk,\r\n  output [1:0] R0_data_takens,\r\n  output [13:0] R0_data_history,\r\n  output [13:0] R0_data_info,\r\n  input  [4:0] W0_addr,\r\n  input   W0_en,\r\n  input   W0_clk,\r\n  input  [1:0] W0_data_takens,\r\n  input  [13:0] W0_data_history,\r\n  input  [13:0] W0_data_info,\r\n  input   W0_mask_takens,\r\n  input   W0_mask_history,\r\n  input   W0_mask_info\r\n);\r\n  wire [4:0] entries_info2_ext_R0_addr;\r\n  wire  entries_info2_ext_R0_en;\r\n  wire  entries_info2_ext_R0_clk;\r\n  wire [29:0] entries_info2_ext_R0_data;\r\n  wire [4:0] entries_info2_ext_W0_addr;\r\n  wire  entries_info2_ext_W0_en;\r\n  wire  entries_info2_ext_W0_clk;\r\n  wire [29:0] entries_info2_ext_W0_data;\r\n  wire [2:0] entries_info2_ext_W0_mask;\r\n  wire [27:0] GEN_0;\r\n  wire [1:0] GEN_1;\r\n  entries_info2_ext entries_info2_ext (\r\n    .R0_addr(entries_info2_ext_R0_addr),\r\n    .R0_en(entries_info2_ext_R0_en),\r\n    .R0_clk(entries_info2_ext_R0_clk),\r\n    .R0_data(entries_info2_ext_R0_data),\r\n    .W0_addr(entries_info2_ext_W0_addr),\r\n    .W0_en(entries_info2_ext_W0_en),\r\n    .W0_clk(entries_info2_ext_W0_clk),\r\n    .W0_data(entries_info2_ext_W0_data),\r\n    .W0_mask(entries_info2_ext_W0_mask)\r\n  );\r\n  assign R0_data_takens = entries_info2_ext_R0_data[29:28];\r\n  assign R0_data_history = entries_info2_ext_R0_data[27:14];\r\n  assign R0_data_info = entries_info2_ext_R0_data[13:0];\r\n  assign entries_info2_ext_R0_addr = R0_addr;\r\n  assign entries_info2_ext_R0_en = R0_en;\r\n  assign entries_info2_ext_R0_clk = R0_clk;\r\n  assign entries_info2_ext_W0_addr = W0_addr;\r\n  assign entries_info2_ext_W0_en = W0_en;\r\n  assign entries_info2_ext_W0_clk = W0_clk;\r\n  assign entries_info2_ext_W0_data = {W0_data_takens,GEN_0};\r\n  assign entries_info2_ext_W0_mask = {W0_mask_takens,GEN_1};\r\n  assign GEN_0 = {W0_data_history,W0_data_info};\r\n  assign GEN_1 = {W0_mask_history,W0_mask_info};\r\nendmodule\r\n```"}}
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