{"action":"created","issue":{"url":"https://api.github.com/repos/ucb-bar/chisel/issues/629","labels_url":"https://api.github.com/repos/ucb-bar/chisel/issues/629/labels{/name}","comments_url":"https://api.github.com/repos/ucb-bar/chisel/issues/629/comments","events_url":"https://api.github.com/repos/ucb-bar/chisel/issues/629/events","html_url":"https://github.com/ucb-bar/chisel/issues/629","id":125349489,"number":629,"title":"BlackBox submodules instantiation","user":{"login":"mcieplucha","id":16589813,"avatar_url":"https://avatars.githubusercontent.com/u/16589813?v=3","gravatar_id":"","url":"https://api.github.com/users/mcieplucha","html_url":"https://github.com/mcieplucha","followers_url":"https://api.github.com/users/mcieplucha/followers","following_url":"https://api.github.com/users/mcieplucha/following{/other_user}","gists_url":"https://api.github.com/users/mcieplucha/gists{/gist_id}","starred_url":"https://api.github.com/users/mcieplucha/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mcieplucha/subscriptions","organizations_url":"https://api.github.com/users/mcieplucha/orgs","repos_url":"https://api.github.com/users/mcieplucha/repos","events_url":"https://api.github.com/users/mcieplucha/events{/privacy}","received_events_url":"https://api.github.com/users/mcieplucha/received_events","type":"User","site_admin":false},"labels":[],"state":"closed","locked":false,"assignee":null,"milestone":null,"comments":3,"created_at":"2016-01-07T08:36:05Z","updated_at":"2016-01-11T07:56:27Z","closed_at":"2016-01-11T07:56:27Z","body":"Hello, \r\n\r\nI would like to instantiate a submodule which is an already existing Verilog block.\r\nHere is my code:\r\n```scala\r\nclass HelloModule extends Module {\r\n  val io = new Bundle { \r\n    val datain = UInt(INPUT, 128)\r\n    val datain_valid = Bool(INPUT)\r\n    val dataout = UInt(OUTPUT, 128)\r\n    val dataout_valid = Bool(OUTPUT)\r\n  }\r\n  val submodule = new Submodule\r\n  //val submoduleIO = new SubmoduleIO\r\n\r\n  val state_reg = Reg(init = UInt(0, width = 128))\r\n  when (io.datain_valid) { \r\n    state_reg := io.datain\r\n  } .otherwise { \r\n    state_reg := submodule.io.s_output\r\n  } \r\n\r\n  submodule.io.s_input := state_reg\r\n\r\n  io.dataout := state_reg\r\n}\r\n\r\nclass SubmoduleIO extends Bundle { \r\n  val s_input = UInt(INPUT,  128) \r\n  val s_output = UInt(OUTPUT, 128) \r\n} \r\n\r\nclass Submodule extends BlackBox { \r\n  val io = new SubmoduleIO()\r\n} \r\n```\r\n\r\nHowever I am getting the following error:\r\n\r\n```\r\n[error] hello.scala:22: assigning to your own input port /*? in < (class Hello.Submodule)>*/ Chisel.UInt(INPUT, width=128, connect to 0 inputs: ()) RHS: /*? in < (class Hello.Submodule)>*/ Chisel.UInt(OUTPUT, width=None, connect to 1 inputs: (?[Chisel.RegReset] in Hello.Submodule)) in class Hello.HelloModule\r\n[error] hello.scala:24: assigning to a non parent module's output port: /*? in < (class Hello.HelloModule)>*/ Chisel.UInt(OUTPUT, width=128, connect to 0 inputs: ()) RHS: /*? in < (class Hello.Submodule)>*/ Chisel.UInt(OUTPUT, width=None, connect to 1 inputs: (?[Chisel.RegReset] in Hello.Submodule)) in class Hello.HelloModule\r\nRe-running Chisel in debug mode to obtain erroneous line numbers...\r\n[error] hcl.scala:203: Hello.Submodule was not properly wrapped into a module() call. in class Chisel.BlackBox\r\n[error] hello.scala:22: assigning to your own input port /*? in < (class Hello.Submodule)>*/ Chisel.UInt(INPUT, width=128, connect to 0 inputs: ()) RHS: /*? in < (class Hello.Submodule)>*/ Chisel.UInt(OUTPUT, width=None, connect to 1 inputs: (?[Chisel.RegReset] in Hello.Submodule)) in class Hello.HelloModule\r\n[error] hello.scala:24: assigning to a non parent module's output port: /*? in < (class Hello.HelloModule)>*/ Chisel.UInt(OUTPUT, width=128, connect to 0 inputs: ()) RHS: /*? in < (class Hello.Submodule)>*/ Chisel.UInt(OUTPUT, width=None, connect to 1 inputs: (?[Chisel.RegReset] in Hello.Submodule)) in class Hello.HelloModule\r\n[error] (run-main-0) java.lang.IllegalStateException: CODE HAS 3 ERRORS and 0 WARNINGS\r\njava.lang.IllegalStateException: CODE HAS 3 ERRORS and 0 WARNINGS\r\n\tat Chisel.ChiselError$.checkpoint(ChiselError.scala:158)\r\n\tat Chisel.Backend.elaborate(Backend.scala:826)\r\n\tat Chisel.VerilogBackend.elaborate(Verilog.scala:729)\r\n\tat Chisel.Driver$.execute(Driver.scala:93)\r\n\tat Chisel.Driver$.apply(Driver.scala:41)\r\n\tat Chisel.Driver$.apply(Driver.scala:46)\r\n\tat Chisel.Driver$.apply(Driver.scala:52)\r\n\tat Chisel.chiselMain$.apply(hcl.scala:63)\r\n\tat Chisel.chiselMainTest$.apply(hcl.scala:76)\r\n\tat Hello.Hello$.main(hello.scala:44)\r\n\tat Hello.Hello.main(hello.scala)\r\n\tat sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)\r\n\tat sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:57)\r\n\tat sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)\r\n\tat java.lang.reflect.Method.invoke(Method.java:606)\r\n[trace] Stack trace suppressed: run last compile:run for the full output.\r\njava.lang.RuntimeException: Nonzero exit code: 1\r\n\tat scala.sys.package$.error(package.scala:27)\r\n[trace] Stack trace suppressed: run last compile:run for the full output.\r\n[error] (compile:run) Nonzero exit code: 1\r\n```\r\n\r\n1. Any ideas what may be wrong here? Could you please add a description of a similar case in the manual?\r\n2. Is it possible to add a high-level functionality of the BlackBox submodule (assuming the HDL already exists and doesn't need to be generated) for testing purpose? \r\n\r\nThanks for help.\r\n"},"comment":{"url":"https://api.github.com/repos/ucb-bar/chisel/issues/comments/170458028","html_url":"https://github.com/ucb-bar/chisel/issues/629#issuecomment-170458028","issue_url":"https://api.github.com/repos/ucb-bar/chisel/issues/629","id":170458028,"user":{"login":"mcieplucha","id":16589813,"avatar_url":"https://avatars.githubusercontent.com/u/16589813?v=3","gravatar_id":"","url":"https://api.github.com/users/mcieplucha","html_url":"https://github.com/mcieplucha","followers_url":"https://api.github.com/users/mcieplucha/followers","following_url":"https://api.github.com/users/mcieplucha/following{/other_user}","gists_url":"https://api.github.com/users/mcieplucha/gists{/gist_id}","starred_url":"https://api.github.com/users/mcieplucha/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/mcieplucha/subscriptions","organizations_url":"https://api.github.com/users/mcieplucha/orgs","repos_url":"https://api.github.com/users/mcieplucha/repos","events_url":"https://api.github.com/users/mcieplucha/events{/privacy}","received_events_url":"https://api.github.com/users/mcieplucha/received_events","type":"User","site_admin":false},"created_at":"2016-01-11T07:56:27Z","updated_at":"2016-01-11T07:56:27Z","body":"Thank you for explanations!"}}