{"push_id":1297196012,"size":22,"distinct_size":0,"ref":"refs/heads/more_utils_cleanups","head":"4cb46ca17da26c7ccc0b66a6be489a49fb2e9173","before":"95d0e01e595aeb17e33ad4d7fb1566ea8fe3590e","commits":[{"sha":"20ff9c96a7c07df8e0cb91444f223384261d35fe","author":{"name":"Angie Wang","email":"e8116d93003241dffa3ed90cf8fce7e86db8bd1f@gmail.com"},"message":"Bug fix -- remove all empty expressions after ReplSeqMem passes (#294)\n\n* Bug fix -- remove all empty expressions after ReplSeqMem passes\r\n\r\n* Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage)","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/20ff9c96a7c07df8e0cb91444f223384261d35fe"},{"sha":"803ccfb1bc44dba88edf0ae9755ec13cbc9192d9","author":{"name":"azidar","email":"be54013606a403c854c87d076d7f638d04be7db1@gmail.com"},"message":"Fixed bug where nodes of Invalids where created","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/803ccfb1bc44dba88edf0ae9755ec13cbc9192d9"},{"sha":"9e7ce6366454347e0ad912c7da0252070e5bb4a1","author":{"name":"azidar","email":"be54013606a403c854c87d076d7f638d04be7db1@gmail.com"},"message":"Added test to check invalid bug was fixed","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/9e7ce6366454347e0ad912c7da0252070e5bb4a1"},{"sha":"00bef01b6df158939406f3e744cbdda544823ae5","author":{"name":"Donggyu","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"Merge pull request #247 from ucb-bar/fix-invalid\n\nBugfix: ExpandWhen was emitting WInvalid()","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/00bef01b6df158939406f3e744cbdda544823ae5"},{"sha":"4702bf9f257f954e19d1441b21e737f951ccfbcc","author":{"name":"jackkoenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@eecs.berkeley.edu"},"message":"Rework map functions as class methods\n\nChanged code from match statements in Mappers.scala to methods on the various\nIR classes. This allows custom IR nodes to implement the mapper functions and\nthus work (ie. not match error) when map is called on them.\n\nThis also should have a marginal performance increase because of use of virtual\nfunction calls rather than match statements.","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/4702bf9f257f954e19d1441b21e737f951ccfbcc"},{"sha":"3847e88e0863aaa6db188b3e8792a35cb86dde22","author":{"name":"jackkoenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@eecs.berkeley.edu"},"message":"Change Mappers to Value Classes","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/3847e88e0863aaa6db188b3e8792a35cb86dde22"},{"sha":"066dc5010a9ebaed276b064451e259318052865e","author":{"name":"Donggyu","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"Merge pull request #266 from ucb-bar/revamp-mappers\n\nRevamp mappers","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/066dc5010a9ebaed276b064451e259318052865e"},{"sha":"117d82b38cc49c53422fe77e5c697792faaa6486","author":{"name":"jackkoenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@eecs.berkeley.edu"},"message":"Add unapply for GroundType","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/117d82b38cc49c53422fe77e5c697792faaa6486"},{"sha":"7f12a07d941bd08749ef350654fe9a324b882a6b","author":{"name":"jackkoenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@eecs.berkeley.edu"},"message":"Change bitWidth to support ClockType\n\nMatch on GroundType instead of UIntType and SIntType","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/7f12a07d941bd08749ef350654fe9a324b882a6b"},{"sha":"6c93f5e688554ff3432715d206351d2d84341eed","author":{"name":"jackkoenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@eecs.berkeley.edu"},"message":"Change Legalize Shift Right to respect SInt\n\nFix bug where Legalize was generating a bit select for SInts without then\ncasting to SInt\n\nFixes #169","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/6c93f5e688554ff3432715d206351d2d84341eed"},{"sha":"f7dd234f7c5a2dc03c42640db11b1d6509108643","author":{"name":"Jack","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Change Legalize Connect to respect SInt\n\nLegalize will wrap the rhs of a connect statement with a bit select primop if\nthe lhs is of smaller width than the rhs. This bit select is now wrapped in a\nasSInt cast if the original rhs was an SInt so that is has the correct type.\n\nFixes #173","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/f7dd234f7c5a2dc03c42640db11b1d6509108643"},{"sha":"9edf656e11084958d9e90807a4740a57b83babfe","author":{"name":"Jack","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Legalize bit select. Run Legalize after PadWidths.\n\nBit selecting a literal resulted in invalid Verilog. Legalize now deals with\nthis by replacing any bits select of UInt or SInt literals with a new literal\ncomposed of the selected bits. Legalize also is now run after PadWidths because\nthat pass introduces this issue.\n\nFixes #170","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/9edf656e11084958d9e90807a4740a57b83babfe"},{"sha":"654f1130b604d74c0a194b2598d70111583b442e","author":{"name":"Jack","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Cast bit select of SInt in PadWidths to SInt\n\nFixes #172","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/654f1130b604d74c0a194b2598d70111583b442e"},{"sha":"5e62c6ba87e398509c1bc7a3d987c7c2e0f7abc4","author":{"name":"Jack","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Add legalization of pad operation on literals.\n\nPerforming a pad on SInt literals results in linting warnings in Verilator.\nThis commit replaces pad operations on literal values with a literal of the\ncorrect width.","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/5e62c6ba87e398509c1bc7a3d987c7c2e0f7abc4"},{"sha":"9a68008856f390bdc3be858f9cce5ed484cdb68f","author":{"name":"Jack","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Add LegalizeSpec for testing Verilog Legalization pass","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/9a68008856f390bdc3be858f9cce5ed484cdb68f"},{"sha":"ad36a1216f52bc01a27dac93cfd8cd42beb84c73","author":{"name":"Jack Koenig","email":"0799805189c2312be340cd4ef604cf7ae0440452@gmail.com"},"message":"Merge pull request #296 from ucb-bar/fix-bits-type-take3\n\nFix bits type","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/ad36a1216f52bc01a27dac93cfd8cd42beb84c73"},{"sha":"b8ee3179ed8070211c95ecbcceda0f7dbf635a13","author":{"name":"Donggyu Kim","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"clean up MemUtils","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/b8ee3179ed8070211c95ecbcceda0f7dbf635a13"},{"sha":"62d97c3aae263b1cd333fdc884422d0099dc5cf1","author":{"name":"Donggyu Kim","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"MemPortUtils: return correct memory types","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/62d97c3aae263b1cd333fdc884422d0099dc5cf1"},{"sha":"dcca7509127e22f1cdcaa916be7538e85ab8da2d","author":{"name":"Donggyu Kim","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"remove Utils.{mapr, get_name} and fix spaces","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/dcca7509127e22f1cdcaa916be7538e85ab8da2d"},{"sha":"a38930a841cf4f328c81bd65844eee5e0fa24b54","author":{"name":"Donggyu Kim","email":"4cc161c8b7af6404ba40a421c9259e24d8073212@eecs.berkeley.edu"},"message":"use MemPortUtils.memType for DefMemory","distinct":false,"url":"https://api.github.com/repos/zizztux/firrtl/commits/a38930a841cf4f328c81bd65844eee5e0fa24b54"}]}
{"actor":{"display_login":"zizztux"}}