{"push_id":1127403922,"size":53,"distinct_size":53,"ref":"refs/heads/master","head":"fc15b9beed05dec6cc092c265042381a0eadb0e9","before":"ec8fb48ce98987065493b27422200897cf0909f8","commits":[{"sha":"074596c0b5f4e9a3642a3159a9fc7f8b8064c18a","author":{"email":"1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@nxp.com","name":"Shengzhou Liu"},"message":"armv8/ls1043: Add workaround for DDR erratum A-008850\n\nBarrier transactions from CCI400 need to be disabled till\nthe DDR is configured, otherwise it may lead to system hang.\nThe patch adds workaround to fix the erratum.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/074596c0b5f4e9a3642a3159a9fc7f8b8064c18a"},{"sha":"4a68489e12313a7fa8740463dee0eea2985eb563","author":{"email":"1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@nxp.com","name":"Shengzhou Liu"},"message":"drivers/ddr/fsl: update workaround for erratum A-008511\n\nPer the latest erratum document, update step 4 and step 8, only\nDEBUG_29[21] is changed, all other bits should not be changed.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/4a68489e12313a7fa8740463dee0eea2985eb563"},{"sha":"5fc62fe57097e195a8047859cd3c278a5d6790b6","author":{"email":"1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@nxp.com","name":"Shengzhou Liu"},"message":"driver/ddr/fsl: Add workaround for erratum A-009801\n\nThe initial training for the DDRC may provide results that are not\noptimized. The workaround provides better read timing margins.\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/5fc62fe57097e195a8047859cd3c278a5d6790b6"},{"sha":"aa7a2226b5a7829915d189d727ee9320dc3a198b","author":{"email":"1404ba22ec6d20cf6fb19ba4d38ae7b07053223f@nxp.com","name":"Shengzhou Liu"},"message":"armv8/ls2080ardb: Update DDR timing to support more UDIMMs\n\nOptimize DDR timing for good margins to support new Transcend\nand Apacer DDR4 UDIMM besides current Micron UDIMM.\n\nVerified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with\nfollowing UDIMM on LS2080ARDB.\n - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z\n - Apacer UDIMM: 78.C1GM4.AF10B\n - Transcend UDIMM: TS1GLH72V1H\n\nSigned-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/aa7a2226b5a7829915d189d727ee9320dc3a198b"},{"sha":"6f3819fe30763bd0d0515997eb4d4fece06abb56","author":{"email":"d4ada725af1db3bc8cc61ece0444105e03a7748f@nxp.com","name":"Prabhakar Kushwaha"},"message":"armv8: ls2080a: Update MAINTAINERS file\n\nUpdate MAINTAINERS file for ls2080aqds and ls2080ardb platforms.\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/6f3819fe30763bd0d0515997eb4d4fece06abb56"},{"sha":"f13c99c2a265d0586702523fab56a3562de31f86","author":{"email":"9cd4fe7678e1630676677a8799e6ca36cabb4300@nxp.com","name":"Alex Porosanu"},"message":"armv8/fdt: add fixup_crypto_node\n\nFor Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in\norder to update the SEC internal version (aka SEC ERA). This patch\nadds the same functionality to the ARMv8 SoCs.\n\nSigned-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/f13c99c2a265d0586702523fab56a3562de31f86"},{"sha":"bf9bffa9784411ba743b127adc031bcb6e27735d","author":{"email":"8590e40ef5cb6355794d7302977c18b721b9b0a7@nxp.com","name":"Yuan Yao"},"message":"spi: fsl_qspi: Fix issues on arm64\n\nThe address value and size value get from dts \"reg\" property have\ntype of u64 on arm64. If we assign those values to \"u32\" variables,\ndriver can't work correctly. Converting the type of those variables\nto fdt_xxx_t.\n\nSigned-off-by: Yuan Yao <yao.yuan@nxp.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/bf9bffa9784411ba743b127adc031bcb6e27735d"},{"sha":"4e14741833607f49eaccdfd4add9cb39e103c2db","author":{"email":"8590e40ef5cb6355794d7302977c18b721b9b0a7@nxp.com","name":"Yuan Yao"},"message":"spi: fsl_qspi: Assign AMBA mem according CS num in dts\n\nQSPI controller automatic enable the chipselect signal according the\ndest AMBA memory address. Now we distribute the AMBA memory zone\naveragely to every chipselect slave device according chipselect\nnumbers got from dts node.\n\nSigned-off-by: Yuan Yao <yao.yuan@nxp.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/4e14741833607f49eaccdfd4add9cb39e103c2db"},{"sha":"febffe8dd1c7ba841890eec578b050bb6faa3273","author":{"email":"8590e40ef5cb6355794d7302977c18b721b9b0a7@nxp.com","name":"Yuan Yao"},"message":"spi: fsl_qspi: Enable Spansion S25FS-S family flashes\n\nThe flash type of LS2085AQDS QSPI is S25FS256S. It has special write\nany device register command and read any device register command.\nThis patch enable support for those commands.\n\nSigned-off-by: Yuan Yao <yao.yuan@nxp.com>\nSigned-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/febffe8dd1c7ba841890eec578b050bb6faa3273"},{"sha":"80c1bfd2332e71dfe669cac53ba06b7435a7ca39","author":{"email":"8590e40ef5cb6355794d7302977c18b721b9b0a7@nxp.com","name":"Yuan Yao"},"message":"sf: Disable 4-KB erase command for SPANSION S25FS-S family\n\nThe S25FS-S family physical sectors may be configured as a hybrid\ncombination of eight 4-kB parameter sectors at the top or bottom\nof the address space with all but one of the remaining sectors\nbeing uniform size.\nThe default status of the flash is in this hybrid architecture.\nThe parameter sectors and the uniform sectors have different erase\ncommands.\nThis patch disable the hybrid sector architecture then the flash will\nhas uniform sector size and uniform erase command.\nThis configuration is temporary, the flash will revert to hybrid\narchitecture after power on reset.\n\nSigned-off-by: Yuan Yao <yao.yuan@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/80c1bfd2332e71dfe669cac53ba06b7435a7ca39"},{"sha":"87e566d77347173cc901e5c9cd325c5d83f65f7e","author":{"email":"8590e40ef5cb6355794d7302977c18b721b9b0a7@nxp.com","name":"Yuan Yao"},"message":"armv8/ls1043a: update the node for QSPI support\n\nThe address value and size value set for QSPI dts node \"reg\"\nproperty have type of u64 on arm64.\n\nSigned-off-by: Yuan Yao <yao.yuan@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/87e566d77347173cc901e5c9cd325c5d83f65f7e"},{"sha":"bcb55f67f22b297d6c10e039bfcef9847a20fbfb","author":{"email":"09e77f088c38d86343c58e9859f6391bfa03fa8a@nxp.com","name":"Aneesh Bansal"},"message":"armv8: ls2080: enable sec_init in U-Boot\n\nDefine CONFIG_FSL_CAAM for LS2080 which would enable\ncall to sec_init() during U-Boot.\n\nSigned-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/bcb55f67f22b297d6c10e039bfcef9847a20fbfb"},{"sha":"7ad9cc969b00cd5e238f4a194f0e974d74706b8e","author":{"email":"d4ada725af1db3bc8cc61ece0444105e03a7748f@nxp.com","name":"Prabhakar Kushwaha"},"message":"armv8: ls2080a: update eth prime\n\nAs per new PHY framework, DPNI naming convetion is no more used.\nUse new naming convention.\n\nSigned-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/7ad9cc969b00cd5e238f4a194f0e974d74706b8e"},{"sha":"acb8f5e914814ac6c697edb86701958da251a223","author":{"email":"d44da55a283b3f67fec472e76af7093c7c6afeb9@freescale.com","name":"Alison Wang"},"message":"armv8: fsl-layerscape: Remove unnecessary flushing dcache\n\nAs the issue about the stack will get corrupted when switching between\nthe early and final mmu tables is fixed by commit 70e21b064, the\nworkaround to flush dcache is unnecessary and should be removed.\n\nSigned-off-by: Alison Wang <alison.wang@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/acb8f5e914814ac6c697edb86701958da251a223"},{"sha":"15b96ad8318d8670d3a776e72dbf8edaca74e4a7","author":{"email":"bcacaa5f449d5e38cf05612cb93a0d5cff74d4c0@provenrun.com","name":"Vincent Siles"},"message":"arm: Fix SCFG ICID reg addresses\n\nOn the LS102x boards, in order to initialize the ICID values of\nmasters, the dev_stream_id array holds absolute offsets from the\nbase of SCFG.\n\nIn ls102xa_config_ssmu_stream_id, the base pointer is cast to\nuint32_t * before adding the offset, leading to an invalid address.\nCasting it to void * solves the issue.\n\nSigned-off-by: Vincent Siles <vincent.siles@provenrun.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/15b96ad8318d8670d3a776e72dbf8edaca74e4a7"},{"sha":"12cbf20d78f93c86e287d86ff863926e5cde9355","author":{"email":"bcacaa5f449d5e38cf05612cb93a0d5cff74d4c0@provenrun.com","name":"Vincent Siles"},"message":"arm: uniform usage of u32 in ls102x caam config\n\nMix usage of uint32_t and u32 fixed in favor of u32.\n\nSigned-off-by: Vincent Siles <vincent.siles@provenrun.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/12cbf20d78f93c86e287d86ff863926e5cde9355"},{"sha":"869bf86811a7c942dc48b294d5c0442b1f57ab53","author":{"email":"ad89704699a1b2a742f83944381f915361e5f46a@nxp.com","name":"Qianyu Gong"},"message":"armv8/ls1043ardb: fix the limitation of using 'cpld reset'\n\nThe current 'cpld reset' will just write global_rst register\nbut couldn't switch to NOR boot if the board's switches are\nfor NAND/SD boot. So need to write rcw source registers for\nNOR boot as well.\n\nSigned-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/869bf86811a7c942dc48b294d5c0442b1f57ab53"},{"sha":"1297cdb452fcdc6e7149c6761e43629f9c732010","author":{"email":"ad89704699a1b2a742f83944381f915361e5f46a@nxp.com","name":"Qianyu Gong"},"message":"armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabled\n\nIFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS.\nSo this patch could fix 'sync abort' caused by autoboot that tries to\naccess IFC address.\n\nSigned-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/1297cdb452fcdc6e7149c6761e43629f9c732010"},{"sha":"ec93abe6f722e6e0103f96ee01bcd376e246f111","author":{"email":"ad89704699a1b2a742f83944381f915361e5f46a@nxp.com","name":"Qianyu Gong"},"message":"armv8: ls1043a: remove redundant code in board files\n\ngd->env_addr will be initialized in env_init() in\ncommon/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.\nSo no need to do it again.\n\nSigned-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/ec93abe6f722e6e0103f96ee01bcd376e246f111"},{"sha":"9718650f8c37fe53727bde26ffc0ecba814008b5","author":{"email":"ad89704699a1b2a742f83944381f915361e5f46a@nxp.com","name":"Qianyu Gong"},"message":"armv8: ls1043ardb: fix types of variables\n\nUsing u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.\n\nSigned-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>\nReviewed-by: York Sun <york.sun@nxp.com>","distinct":true,"url":"https://api.github.com/repos/u-boot/u-boot/commits/9718650f8c37fe53727bde26ffc0ecba814008b5"}]}
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