{"push_id":1175541651,"size":3,"distinct_size":3,"ref":"refs/heads/RV32IB","head":"8d331d5d31d9b5c9c6a1a1f2218284527f18dcc2","before":"1c3be3cf546a09a0b9c0dd234b69d616ea0b5416","commits":[{"sha":"ef0510b5fd71d2412585e5015ef901a92bc69346","author":{"name":"Rafael Auler","email":"f32e439dae7152e0f2a5a2a8cfb8d472929f667a@gmail.com"},"message":"Remove trailing curly braces in riscv_isa.cpp","distinct":true,"url":"https://api.github.com/repos/Pavani14/RISCV-processor/commits/ef0510b5fd71d2412585e5015ef901a92bc69346"},{"sha":"fb702f49b4f1a41609494771c98832ddab39887f","author":{"name":"Rafael Auler","email":"f32e439dae7152e0f2a5a2a8cfb8d472929f667a@gmail.com"},"message":"[syscalls] Add initial pair of syscalls files to the model\n\nAdd riscv_syscalls.H and matching riscv_syscalls.cpp file in order to\nmake the model successfully compile with gcc and generate the simulator.\nThese files were copied from the MIPS32r2 model with trivial changes to\nmatch the RISCV model. However, we still need to change them to match\nthe correct implementation of RISCV, since it is different from MIPS.","distinct":true,"url":"https://api.github.com/repos/Pavani14/RISCV-processor/commits/fb702f49b4f1a41609494771c98832ddab39887f"},{"sha":"8d331d5d31d9b5c9c6a1a1f2218284527f18dcc2","author":{"name":"Pavani14","email":"2a1a09d6312bdb7a17e14650fc0e5b64fb543edd@iiitd.ac.in"},"message":"Merge pull request #2 from rafaelauler/RV32IB\n\nChangeset to make the model past the compilation phase","distinct":true,"url":"https://api.github.com/repos/Pavani14/RISCV-processor/commits/8d331d5d31d9b5c9c6a1a1f2218284527f18dcc2"}]}
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