{"push_id":1351658695,"size":23,"distinct_size":23,"ref":"refs/heads/atomic-6","head":"d14f781ffdf7f0d9ec967ff1447f6e8f80c72713","before":"527a6fedbcb9359cf5fef689b7b53633a9a54e2d","commits":[{"sha":"bf7dd64cc3af30805e1c424bd3dbfc27f9ccdbc1","author":{"name":"Richard Henderson","email":"f254276749ad35c7bae5bcbe6d11ac32818dbd7d@twiddle.net"},"message":"tcg: Add atomic helpers\n\nAdd all of cmpxchg, op_fetch, fetch_op, and xchg.\nHandle both endian-ness, and sizes up to 8.\nHandle expanding non-atomically, when emulating in serial.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/bf7dd64cc3af30805e1c424bd3dbfc27f9ccdbc1"},{"sha":"ec526997177a920432f135720ce4097a04957dff","author":{"name":"Richard Henderson","email":"f254276749ad35c7bae5bcbe6d11ac32818dbd7d@twiddle.net"},"message":"tcg: Add atomic128 helpers\n\nForce the use of cmpxchg16b on x86_64.\n\nWikipedia suggests that only very old AMD64 (circa 2004) did not have\nthis instruction.  Further, it's required by Windows 8 so no new cpus\nwill ever omit it.\n\nIf we truely care about these, then we could check this at startup time\nand then avoid executing paths that use it.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/ec526997177a920432f135720ce4097a04957dff"},{"sha":"ccfc41c6ad9da4773cdaf6f20b62839039f41b4e","author":{"name":"Richard Henderson","email":"f254276749ad35c7bae5bcbe6d11ac32818dbd7d@twiddle.net"},"message":"tcg: Add CONFIG_ATOMIC64\n\nAllow qemu to build on 32-bit hosts without 64-bit atomic ops.\n\nEven if we only allow 32-bit hosts to multi-thread emulate 32-bit\nguests, we still need some way to handle the 32-bit guest using a\n64-bit atomic operation.  Do so by dropping back to single-step.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/ccfc41c6ad9da4773cdaf6f20b62839039f41b4e"},{"sha":"e947ada710611b602d5801159515daac13d508c2","author":{"name":"Richard Henderson","email":"f254276749ad35c7bae5bcbe6d11ac32818dbd7d@twiddle.net"},"message":"tcg: Emit barriers with parallel_cpus\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/e947ada710611b602d5801159515daac13d508c2"},{"sha":"b06a61e618d5232620b12d3c0d1a211767da9021","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate LOCK'ed cmpxchg using cmpxchg helpers\n\nThe diff here is uglier than necessary. All this does is to turn\n\nFOO\n\ninto:\n\nif (s->prefix & PREFIX_LOCK) {\n  BAR\n} else {\n  FOO\n}\n\nwhere FOO is the original implementation of an unlocked cmpxchg.\n\n[rth: Adjust unlocked cmpxchg to use movcond instead of branches.\nAdjust helpers to use atomic helpers.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-6-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/b06a61e618d5232620b12d3c0d1a211767da9021"},{"sha":"345a0d5e0bcf29279e3a00bd588c574f8ba5e605","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate LOCK'ed OP instructions using atomic helpers\n\n[rth: Eliminate some unnecessary temporaries.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-13-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/345a0d5e0bcf29279e3a00bd588c574f8ba5e605"},{"sha":"7743e5b4b9465c191023e121f4c67cc0d41c8758","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate LOCK'ed INC using atomic helper\n\n[rth: Merge gen_inc_locked back into gen_inc to share cc update.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-14-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/7743e5b4b9465c191023e121f4c67cc0d41c8758"},{"sha":"df2c008fcdfd20f366ab1c99508ce9fd83858fff","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate LOCK'ed NOT using atomic helper\n\n[rth: Avoid qemu_load that's redundant with the atomic op.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-15-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/df2c008fcdfd20f366ab1c99508ce9fd83858fff"},{"sha":"65cc36c1e539cfd4d5bd1c20cb0f2b539ea3b986","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate LOCK'ed NEG using cmpxchg helper\n\n[rth: Move redundant qemu_load out of cmpxchg loop.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-16-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/65cc36c1e539cfd4d5bd1c20cb0f2b539ea3b986"},{"sha":"291a4fbdd03557ef27503b185f24adcdb8cbfa45","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate LOCK'ed XADD using atomic helper\n\n[rth: Move load of reg value to common location.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-17-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/291a4fbdd03557ef27503b185f24adcdb8cbfa45"},{"sha":"aa585da3583b0de604c13bb8bbf73deea56bad13","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate LOCK'ed BTX ops using atomic helpers\n\n[rth: Avoid redundant qemu_ld in locked case.  Fix previously unnoticed\nincorrect zero-extension of address in register-offset case.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-18-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/aa585da3583b0de604c13bb8bbf73deea56bad13"},{"sha":"90d3750aa0df4bca7490bbfbcbe5097e5ca88225","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: emulate XCHG using atomic helper\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-19-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/90d3750aa0df4bca7490bbfbcbe5097e5ca88225"},{"sha":"57f23aef0990ced4607fa85c4e1e8075f815811d","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-i386: remove helper_lock()\n\nIt's been superseded by the atomic helpers.\n\nThe use of the atomic helpers provides a significant performance and scalability\nimprovement. Below is the result of running the atomic_add-test microbenchmark with:\n $ x86_64-linux-user/qemu-x86_64 tests/atomic_add-bench -o 5000000 -r $r -n $n\n, where $n is the number of threads and $r is the allowed range for the additions.\n\nThe scenarios measured are:\n- atomic: implements x86' ADDL with the atomic_add helper (i.e. this patchset)\n- cmpxchg: implement x86' ADDL with a TCG loop using the cmpxchg helper\n- master: before this patchset\n\nResults sorted in ascending range, i.e. descending degree of contention.\nY axis is Throughput in Mops/s. Tests are run on an AMD machine with 64\nOpteron 6376 cores.\n\n                atomic_add-bench: 5000000 ops/thread, [0,1] range\n\n  25 ++---------+----------+---------+----------+----------+----------+---++\n     + atomic +-E--+       +         +          +          +          +    |\n     |cmpxchg +-H--+                                                       |\n  20 +Emaster +-N--+                                                      ++\n     ||                                                                    |\n     |++                                                                   |\n     ||                                                                    |\n  15 +++                                                                  ++\n     |N|                                                                   |\n     |+|                                                                   |\n  10 ++|                                                                  ++\n     |+|+                                                                  |\n     | |    -+E+------        +++  ---+E+------+E+------+E+-----+E+------+E|\n     |+E+E+- +++     +E+------+E+--                                        |\n   5 ++|+                                                                 ++\n     |+N+H+---                                 +++                         |\n     ++++N+--+H++----+++   +  +++  --++H+------+H+------+H++----+H+---+--- |\n   0 ++---------+-----H----+---H-----+----------+----------+----------+---H+\n     0          10         20        30         40         50         60\n                                Number of threads\n\n                atomic_add-bench: 5000000 ops/thread, [0,2] range\n\n  25 ++---------+----------+---------+----------+----------+----------+---++\n     ++atomic +-E--+       +         +          +          +          +    |\n     |cmpxchg +-H--+                                                       |\n  20 ++master +-N--+                                                      ++\n     |E|                                                                   |\n     |++                                                                   |\n     ||E                                                                   |\n  15 ++|                                                                  ++\n     |N||                                                                  |\n     |+||                                   ---+E+------+E+-----+E+------+E|\n  10 ++| |        ---+E+------+E+-----+E+---                    +++      +++\n     ||H+E+--+E+--                                                         |\n     |+++++                                                                |\n     | ||                                                                  |\n   5 ++|+H+--                                  +++                        ++\n     |+N+    -                              ---+H+------+H+------          |\n     +  +N+--+H++----+H+---+--+H+----++H+---    +          +    +H+---+--+H|\n   0 ++---------+----------+---------+----------+----------+----------+---++\n     0          10         20        30         40         50         60\n                                Number of threads\n\n                atomic_add-bench: 5000000 ops/thread, [0,8] range\n\n  40 ++---------+----------+---------+----------+----------+----------+---++\n     ++atomic +-E--+       +         +          +          +          +    |\n  35 +cmpxchg +-H--+                                                      ++\n     | master +-N--+               ---+E+------+E+------+E+-----+E+------+E|\n  30 ++|                   ---+E+--   +++                                 ++\n     | |            -+E+---                                                |\n  25 ++E        ---- +++                                                  ++\n     |+++++ -+E+                                                           |\n  20 +E+ E-- +++                                                          ++\n     |H|+++                                                                |\n     |+|                                       +H+-------                  |\n  15 ++H+                                   ---+++      +H+------         ++\n     |N++H+--                         +++---                    +H+------++|\n  10 ++ +++  -       +++           ---+H+                       +++      +H+\n     | |     +H+-----+H+------+H+--                                        |\n   5 ++|                      +++                                         ++\n     ++N+N+--+N++          +         +          +          +          +    |\n   0 ++---------+----------+---------+----------+----------+----------+---++\n     0          10         20        30         40         50         60\n                                Number of threads\n\n               atomic_add-bench: 5000000 ops/thread, [0,128] range\n\n  160 ++---------+---------+----------+---------+----------+----------+---++\n      + atomic +-E--+      +          +         +          +          +    |\n  140 +cmpxchg +-H--+                          +++      +++               ++\n      | master +-N--+                           E--------E------+E+------++|\n  120 ++                                      --|        |      +++       E+\n      |                                     -- +++      +++              ++|\n  100 ++                                   -                              ++\n      |                                +++-                     +++      ++|\n   80 ++                              -+E+    -+H+------+H+------H--------++\n      |                           ----    ----                  +++       H|\n      |            ---+E+-----+E+-  ---+H+                               ++|\n   60 ++     +E+---   +++  ---+H+---                                      ++\n      |    --+++   ---+H+--                                                |\n   40 ++ +E+-+H+---                                                       ++\n      |  +H+                                                               |\n   20 +EE+                                                                ++\n      +N+        +         +          +         +          +          +    |\n    0 ++N-N---N--+---------+----------+---------+----------+----------+---++\n      0          10        20         30        40         50         60\n                                Number of threads\n\n              atomic_add-bench: 5000000 ops/thread, [0,1024] range\n\n  350 ++---------+---------+----------+---------+----------+----------+---++\n      + atomic +-E--+      +          +         +          +          +    |\n  300 +cmpxchg +-H--+                                                    +++\n      | master +-N--+                                           +++       ||\n      |                                                 +++      |    ----E|\n  250 ++                                                 |   ----E----    ++\n      |                                              ----E---    |    ---+H|\n  200 ++                                      -+E+---   +++  ---+H+---    ++\n      |                                   ----         -+H+--              |\n      |                                +E+     +++ ---- +++                |\n  150 ++                            ---+++  ---+H+-                       ++\n      |                          ---  -+H+--                               |\n  100 ++                   ---+E+ ---- +++                                ++\n      |      +++   ---+E+-----+H+-                                         |\n      |     -+E+------+H+--                                                |\n   50 ++ +E+                                                              ++\n      +EE+       +         +          +         +          +          +    |\n    0 ++N-N---N--+---------+----------+---------+----------+----------+---++\n      0          10        20         30        40         50         60\n                                Number of threads\n\n  hi-res: http://imgur.com/a/fMRmq\n\nFor master I stopped measuring master after 8 threads, because there is little\npoint in measuring the well-known performance collapse of a contended lock.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-21-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/57f23aef0990ced4607fa85c4e1e8075f815811d"},{"sha":"59c5992f1a76bb9ebf36b1986cefc4aab2388e2e","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"tests: add atomic_add-bench\n\nWith this microbenchmark we can measure the overhead of emulating atomic\ninstructions with a configurable degree of contention.\n\nThe benchmark spawns $n threads, each performing $o atomic ops (additions)\nin a loop. Each atomic operation is performed on a different cache line\n(assuming lines are 64b long) that is randomly selected from a range [0, $r).\n\n[ Note: each $foo corresponds to a -foo flag ]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\nMessage-Id: <1467054136-10430-20-git-send-email-cota@braap.org>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/59c5992f1a76bb9ebf36b1986cefc4aab2388e2e"},{"sha":"eb6c37d2fb9a4d56d1c816b02fe0d35257ab8ef8","author":{"name":"Richard Henderson","email":"f254276749ad35c7bae5bcbe6d11ac32818dbd7d@twiddle.net"},"message":"target-arm: Rearrange aa32 load and store functions\n\nStop specializing on TARGET_LONG_BITS == 32; unconditionally allocate\na temp and expand with tcg_gen_extu_i32_tl.  Split out gen_aa32_addr,\ngen_aa32_frob64, gen_aa32_ld_i32 and gen_aa32_st_i32 as separate interfaces.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/eb6c37d2fb9a4d56d1c816b02fe0d35257ab8ef8"},{"sha":"f4c895d659b72e33ac7b71dde24c63f56887d1b6","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-arm: emulate LL/SC using cmpxchg helpers\n\nEmulating LL/SC with cmpxchg is not correct, since it can\nsuffer from the ABA problem. Portable parallel code, however,\nis written assuming only cmpxchg--and not LL/SC--is available.\nThis means that in practice emulating LL/SC with cmpxchg is\na viable alternative.\n\nThe appended emulates LL/SC pairs in ARM with cmpxchg helpers.\nThis works in both user and system mode. In usermode, it avoids\npausing all other CPUs to perform the LL/SC pair. The subsequent\nperformance and scalability improvement is significant, as the\nplots below show. They plot the throughput of atomic_add-bench\ncompiled for ARM and executed on a 64-core x86 machine.\n\nHi-res plots: http://imgur.com/a/aNQpB\n\n               atomic_add-bench: 1000000 ops/thread, [0,1] range\n\n  9 ++---------+----------+----------+----------+----------+----------+---++\n    +cmpxchg +-E--+       +          +          +          +          +    |\n  8 +Emaster +-H--+                                                       ++\n    | |                                                                    |\n  7 ++E                                                                   ++\n    | |                                                                    |\n  6 ++++                                                                  ++\n    |  |                                                                   |\n  5 ++ |                                                                  ++\n  4 ++ |                                                                  ++\n    |  |                                                                   |\n  3 ++ |                                                                  ++\n    |   |                                                                  |\n  2 ++  |                                                                 ++\n    |H++E+---                                  +++  ---+E+------+E+------+E|\n  1 +++     +E+-----+E+------+E+------+E+------+E+--   +++      +++       ++\n    ++H+       +    +++   +  +++     ++++       +          +          +    |\n  0 ++--H----H-+-----H----+----------+----------+----------+----------+---++\n    0          10         20         30         40         50         60\n                               Number of threads\n\n                atomic_add-bench: 1000000 ops/thread, [0,2] range\n\n  16 ++---------+----------+---------+----------+----------+----------+---++\n     +cmpxchg +-E--+       +         +          +          +          +    |\n  14 ++master +-H--+                                                      ++\n     | |                                                                   |\n  12 ++|                                                                  ++\n     | E                                                                   |\n  10 ++|                                                                  ++\n     | |                                                                   |\n   8 ++++                                                                 ++\n     |E+|                                                                  |\n     |  |                                                                  |\n   6 ++ |                                                                 ++\n     |   |                                                                 |\n   4 ++  |                                                                ++\n     |  +E+---       +++      +++              +++           ---+E+------+E|\n   2 +H+     +E+------E-------+E+-----+E+------+E+------+E+--            +++\n     + |        +    +++   +         ++++       +          +          +    |\n   0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++\n     0          10         20        30         40         50         60\n                                Number of threads\n\n               atomic_add-bench: 1000000 ops/thread, [0,128] range\n\n  70 ++---------+----------+---------+----------+----------+----------+---++\n     +cmpxchg +-E--+       +         +          +       ++++          +    |\n  60 ++master +-H--+                                 ----E------+E+-------++\n     |                                        -+E+---   +++     +++      +E|\n     |                                +++ ---- +++                       ++|\n  50 ++                       +++  ---+E+-                                ++\n     |                        -E---                                        |\n  40 ++                    ---+++                                         ++\n     |               +++---                                                |\n     |              -+E+                                                   |\n  30 ++      +++----                                                      ++\n     |       +E+                                                           |\n  20 ++ +++--                                                             ++\n     |  +E+                                                                |\n     |+E+                                                                  |\n  10 +E+                                                                  ++\n     +          +          +         +          +          +          +    |\n   0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++\n     0          10         20        30         40         50         60\n                                Number of threads\n\n              atomic_add-bench: 1000000 ops/thread, [0,1024] range\n\n  120 ++---------+---------+----------+---------+----------+----------+---++\n      +cmpxchg +-E--+      +          +         +          +          +    |\n      | master +-H--+                                                    ++|\n  100 ++                                                              ----E+\n      |                                                 +++  ---+E+---   ++|\n      |                                                --E---   +++        |\n   80 ++                                           ---- +++               ++\n      |                                     ---+E+-                        |\n   60 ++                              -+E+--                              ++\n      |                       +++ ---- +++                                 |\n      |                      -+E+-                                         |\n   40 ++              +++----                                             ++\n      |      +++   ---+E+                                                  |\n      |     -+E+---                                                        |\n   20 ++ +E+                                                              ++\n      |+E+++                                                               |\n      +E+        +         +          +         +          +          +    |\n    0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++\n      0          10        20         30        40         50         60\n                                Number of threads\n\n[rth: Enforce alignment for ldrexd.]\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-23-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/f4c895d659b72e33ac7b71dde24c63f56887d1b6"},{"sha":"169747a3cdf9e3cd1f4e1ea540dca84b9650625c","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-arm: emulate SWP with atomic_xchg helper\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-25-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/169747a3cdf9e3cd1f4e1ea540dca84b9650625c"},{"sha":"b3dbf8fdb04f30619180c0d715a8dcb42a767e84","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"target-arm: emulate aarch64's LL/SC using cmpxchg helpers\n\nEmulating LL/SC with cmpxchg is not correct, since it can\nsuffer from the ABA problem. Portable parallel code, however,\nis written assuming only cmpxchg--and not LL/SC--is available.\nThis means that in practice emulating LL/SC with cmpxchg is\na viable alternative.\n\nThe appended emulates LL/SC pairs in aarch64 with cmpxchg helpers.\nThis works in both user and system mode. In usermode, it avoids\npausing all other CPUs to perform the LL/SC pair. The subsequent\nperformance and scalability improvement is significant, as the\nplots below show. They plot the throughput of atomic_add-bench\ncompiled for ARM and executed on a 64-core x86 machine.\n\nHi-res plots: http://imgur.com/a/JVc8Y\n\n                atomic_add-bench: 1000000 ops/thread, [0,1] range\n\n  18 ++---------+----------+---------+----------+----------+----------+---++\n     +cmpxchg +-E--+       +         +          +          +          +    |\n  16 ++master +-H--+                                                      ++\n     ||                                                                    |\n  14 ++                                                                   ++\n     | |                                                                   |\n  12 ++|                                                                  ++\n     | |                                                                   |\n  10 ++++                                                                 ++\n   8 ++E                                                                  ++\n     |+++                                                                  |\n   6 ++ |                                                                 ++\n     |  |                                                                  |\n   4 ++ |                                                                 ++\n     |   |                                                                 |\n   2 +H++E+---                                                            ++\n     + |     +E++----+E+---+--+E+----++E+------+E+------+E++----+E+---+--+E|\n   0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++\n     0          10         20        30         40         50         60\n                                Number of threads\n\n                atomic_add-bench: 1000000 ops/thread, [0,2] range\n\n  18 ++---------+----------+---------+----------+----------+----------+---++\n     +cmpxchg +-E--+       +         +          +          +          +    |\n  16 ++master +-H--+                                                      ++\n     | |                                                                   |\n  14 ++E                                                                  ++\n     | |                                                                   |\n  12 ++|                                                                  ++\n     |+++                                                                  |\n  10 ++ |                                                                 ++\n   8 ++ |                                                                 ++\n     |  |                                                                  |\n   6 ++ |                                                                 ++\n     |   |                                                                 |\n   4 ++  |                                                                ++\n     |  +E+---                                                             |\n   2 +H+     +E+-----+++              +++      +++   ---+E+-----+E+------+++\n     +++        +    +E+---+--+E+----++E+------+E+---   ++++    +++   +  +E|\n   0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++\n     0          10         20        30         40         50         60\n                                Number of threads\n\n               atomic_add-bench: 1000000 ops/thread, [0,128] range\n\n  70 ++---------+----------+---------+----------+----------+----------+---++\n     +cmpxchg +-E--+       +         +          +          +          +    |\n  60 ++master +-H--+                  +++            ---+E+-----+E+------+E+\n     |                        +E+------E-------+E+---                      |\n     |                     ---        +++                                  |\n  50 ++              +++---                                               ++\n     |              -+E+                                                   |\n  40 ++      +++----                                                      ++\n     |        E-                                                           |\n     |      --|                                                            |\n  30 ++   -- +++                                                          ++\n     |  +E+                                                                |\n  20 ++E+                                                                 ++\n     |E+                                                                   |\n     |                                                                     |\n  10 ++                                                                   ++\n     +          +          +         +          +          +          +    |\n   0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++\n     0          10         20        30         40         50         60\n                                Number of threads\n\n              atomic_add-bench: 1000000 ops/thread, [0,1024] range\n\n  160 ++---------+---------+----------+---------+----------+----------+---++\n      +cmpxchg +-E--+      +          +         +          +          +    |\n  140 ++master +-H--+                                           +++      +++\n      |                                                -+E+-----+E+-------E|\n  120 ++                                       +++ ----                  +++\n      |                                +++  ----E--                        |\n  100 ++                              --E---   +++                        ++\n      |                       +++ ---- +++                                 |\n   80 ++                     --E--                                        ++\n      |                  ---- +++                                          |\n      |              -+E+                                                  |\n   60 ++         ---- +++                                                 ++\n      |      +E+-                                                          |\n   40 ++   --                                                             ++\n      |  +E+                                                               |\n   20 +EE+                                                                ++\n      +++        +         +          +         +          +          +    |\n    0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++\n      0          10        20         30        40         50         60\n                                Number of threads\n\n[rth: Rearrange 128-bit cmpxchg helper.  Enforce alignment on LL.]\n\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nMessage-Id: <1467054136-10430-28-git-send-email-cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/b3dbf8fdb04f30619180c0d715a8dcb42a767e84"},{"sha":"891e547434e862d327175e333b25c2dd446ef70e","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"linux-user: remove handling of ARM's EXCP_STREX\n\nThe exception is not emitted anymore.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twidle.net>\nMessage-Id: <1467054136-10430-29-git-send-email-cota@braap.org>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/891e547434e862d327175e333b25c2dd446ef70e"},{"sha":"cdfc6c5a0f6162efd3d0c838c0bb1a0645afea00","author":{"name":"Emilio G. Cota","email":"2ef58f7968325b2e7ec839e83a175e093b7d2b07@braap.org"},"message":"linux-user: remove handling of aarch64's EXCP_STREX\n\nThe exception is not emitted anymore.\n\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nSigned-off-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\nMessage-Id: <1467054136-10430-30-git-send-email-cota@braap.org>","distinct":true,"url":"https://api.github.com/repos/rth7680/qemu/commits/cdfc6c5a0f6162efd3d0c838c0bb1a0645afea00"}]}
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