{"action":"opened","number":4,"pull_request":{"url":"https://api.github.com/repos/mcoquelin-stm32/afboot-stm32/pulls/4","id":81595003,"html_url":"https://github.com/mcoquelin-stm32/afboot-stm32/pull/4","diff_url":"https://github.com/mcoquelin-stm32/afboot-stm32/pull/4.diff","patch_url":"https://github.com/mcoquelin-stm32/afboot-stm32/pull/4.patch","issue_url":"https://api.github.com/repos/mcoquelin-stm32/afboot-stm32/issues/4","number":4,"state":"open","locked":false,"title":"Use SAIPLL in order to provide the USB 48MHz clock","user":{"login":"andreamerello","id":8379186,"avatar_url":"https://avatars.githubusercontent.com/u/8379186?v=3","gravatar_id":"","url":"https://api.github.com/users/andreamerello","html_url":"https://github.com/andreamerello","followers_url":"https://api.github.com/users/andreamerello/followers","following_url":"https://api.github.com/users/andreamerello/following{/other_user}","gists_url":"https://api.github.com/users/andreamerello/gists{/gist_id}","starred_url":"https://api.github.com/users/andreamerello/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/andreamerello/subscriptions","organizations_url":"https://api.github.com/users/andreamerello/orgs","repos_url":"https://api.github.com/users/andreamerello/repos","events_url":"https://api.github.com/users/andreamerello/events{/privacy}","received_events_url":"https://api.github.com/users/andreamerello/received_events","type":"User","site_admin":false},"body":"Hi,\r\n\r\nOn my stm32f469 discovery board AFAICT the USB clock is quite off the nominal value (the ST reference manual mention 48MHz +/-0.25%, while I get more than 51MHz).\r\n\r\nCurrently I could not find any solution to derive a precise 48MHz clock from the main PLL without lowering clocks for the rest of system, so I'm synthesising the USB clock from the SAIPLL.\r\n\r\nThis makes the USB clock to be 48MHz, as it should. Looks like a reasonable solution to you ?\r\n\r\n..I've also a patch for the kernel clk driver in my linux-stm32 repo in order to detect this configuration and modifying accordingly the clk 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