{"push_id":1005901020,"size":11,"distinct_size":11,"ref":"refs/heads/ezchip/ez-for-upstream","head":"e68451c34b532813b037e549347764288e0d7b98","before":"735a95741a58c2f3862385069171d6b396baba96","commits":[{"sha":"3367cdd06dd628f831d3382ebbbe7eaf7c51102d","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: generate jump tables in code section for nps400\n\nWhen code runs from section loaded into fast memory we do not want it to\nuse rodata section from a slow memory for any jump tables.  This commit\nturns on CASE_VECTOR_PC_RELATIVE by default for NPS400 targets, which in\nturn turns on JUMP_TABLES_IN_TEXT_SECTION, which will place the jump\ntables into the code section.\n\nAs a later optimisation we could be smarter about this, only turning on\ninline jump tables when the code section is not the default code\nsection (.text), which we assume is not loaded into fast memory.\n\ngcc/ChangeLog:\n\n\t* config/arc/arc.opt (TARGET_CASE_VECTOR_PC_RELATIVE): Default on\n\tfor NPS400.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/3367cdd06dd628f831d3382ebbbe7eaf7c51102d"},{"sha":"25a8417fd0323d78878b64f02283acf181df52bc","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: Replace rI constraint with r & Cm2 for ld and update insns\n\nIn the load*_update instructions the constraint 'rI' was being used,\nwhich would accept either a register or a signed 12 bit constant.  The\nproblem is that the 32-bit form of ld with update only takes a signed\n9-bit immediate.  As such, some ld instructions could be generated that\nwould, when assembled be 64-bit long, however, GCC believed them to be\n32-bit long.  This error in the length would cause problems during\nbranch shortening.\n\nThe store*_update have the same restrictions on immediate size, however,\nthe patterns for these instructions already only accept 9-bit\nimmediates, and so should be safe.\n\ngcc/ChangeLog:\n\n\t* config/arc/arc.md (*loadqi_update): Replace use of 'rI'\n\tconstraint with separate 'r' and 'Cm2' constraints.\n\t(*load_zeroextendqisi_update): Likewise.\n\t(*load_signextendqisi_update): Likewise.\n\t(*loadhi_update): Likewise.\n\t(*load_zeroextendhisi_update): Likewise.\n\t(*load_signextendhisi_update): Likewise.\n\t(*loadsi_update): Likewise.\n\t(*loadsf_update): Likewise.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/25a8417fd0323d78878b64f02283acf181df52bc"},{"sha":"784abee55cddd8ad0f839747a7deb68028b3b864","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: convert some constraints to define_constraint\n\nThe define_memory_constraint allows for the address operand to be\nreloaded into a base register.  However, for the constraints 'Us<' and\n'Us>', which are used for matching 'push' and 'pop' instructions moving\nthe address into a base register is not helpful.  The constraints then\nshould be define_constraint, not define_memory_constraint.\n\nSimilarly the Usd constraint, used for generating small data area memory\naccesses, can't have its operand loaded into a register as the\nrelocation for small data area symbols only works within ld/st\ninstructions.\n\ngcc/ChangeLog:\n\n\t* config/arc/constraints.md (Usd): Convert to define_constraint.\n\t(Us<): Likewise.\n\t(Us>): Likewise.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/784abee55cddd8ad0f839747a7deb68028b3b864"},{"sha":"d7d24983439bd9a4d537917ac904e7eec07906cc","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: Add support for nps400 cmem xld/xst instructions\n\nThis commit adds support for NPS400 cmem memory sections.  Data to be\nplaced into cmem memory is placed into a section \".cmem\",\n\".cmem_shared\", or \".cmem_private\".\n\nThere are restrictions on how instructions can be used to operate on\ndata held in cmem memory, this is reflected by the introduction of new\noperand constraints (Uex/Ucm), and modifications to some instructions to\nmake use of these constraints.\n\ngcc/ChangeLog:\n\n\t* config/arc/arc.h (SYMBOL_FLAG_CMEM): Define.\n\t(TARGET_NPS400_CMEM_DEFAULT): Provide default definition.\n\t* config/arc/arc.c (arc_address_cost): Return 0 for cmem_address.\n\t(arc_encode_section_info): Set SYMBOL_FLAG_CMEM where indicated.\n\t* config/arc/arc.opt (mcmem): New option.\n\t* config/arc/arc.md (*extendqihi2_i): Add r/Uex alternative,\n\tsupply length for r/m alternative.\n\t(*extendqisi2_ac): Likewise.\n\t(*extendhisi2_i): Add r/Uex alternative, supply length for r/m and\n\tr/Uex alternative.\n\t(movqi_insn): Add r/Ucm and Ucm/?Rac alternatives.\n\t(movhi_insn): Likewise.\n\t(movsi_insn): Add r/Ucm,Ucm/w alternatives.\n\t(*zero_extendqihi2_i): Add r/Ucm alternative.\n\t(*zero_extendqisi2_ac): Likewise.\n\t(*zero_extendhisi2_i): Likewise.\n\t* config/arc/constraints.md (Uex): New memory constraint.\n\t(Ucm): New define_constraint.\n\t* config/arc/predicates.md (long_immediate_loadstore_operand):\n\tReturn 0 for MEM with cmem_address address.\n\t(cmem_address_0): New predicates.\n\t(cmem_address_1): Likewise.\n\t(cmem_address_2): Likewise.\n\t(cmem_address): Likewise.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/arc/cmem-1.c: New file.\n\t* gcc.target/arc/cmem-2.c: New file.\n\t* gcc.target/arc/cmem-3.c: New file.\n\t* gcc.target/arc/cmem-4.c: New file.\n\t* gcc.target/arc/cmem-5.c: New file.\n\t* gcc.target/arc/cmem-6.c: New file.\n\t* gcc.target/arc/cmem-7.c: New file.\n\t* gcc.target/arc/cmem-ld.inc: New file.\n\t* gcc.target/arc/cmem-st.inc: New file.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/d7d24983439bd9a4d537917ac904e7eec07906cc"},{"sha":"90a078f4c7d4a8caeacda49886443bcd23f5d25e","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: Add nps400 bitops support\n\nAdd support for nps400 bit operation instructions.  There's a new flag\n-mbitops that turns this feature on.  There are new instructions, some\nchanges to existing instructions, a new register class to support the\nnew instructions, and some new expand and peephole optimisations.\n\ngcc/ChangeLog:\n\n\t* config/arc/arc.c (arc_conditional_register_usage): Take\n\tTARGET_RRQ_CLASS into account.\n\t(arc_print_operand): Support printing 'p' and 's' operands.\n\t* config/arc/arc.h (TARGET_NPS400_BITOPS_DEFAULT): Provide default\n\tas 0.\n\t(TARGET_RRQ_CLASS): Define.\n\t(IS_POWEROF2_OR_0_P): Define.\n\t* config/arc/arc.md (*movsi_insn): Add w/Clo, w/Chi, and w/Cbi\n\talternatives.\n\t(*tst_movb): New define_insn.\n\t(*tst): Avoid recognition if it could prevent '*tst_movb'\n\tcombination; replace c/CnL with c/Chs alternative.\n\t(*tst_bitfield_tst): New define_insn.\n\t(*tst_bitfield_asr): New define_insn.\n\t(*tst_bitfield): New define_insn.\n\t(andsi3_i): Add Rrq variant.\n\t(extzv): New define_expand.\n\t(insv): New define_expand.\n\t(*insv_i): New define_insn.\n\t(*movb): New define_insn.\n\t(*movb_signed): New define_insn.\n\t(*movb_high): New define_insn.\n\t(*movb_high_signed): New define_insn.\n\t(*movb_high_signed + 1): New define_split pattern.\n\t(*mrgb): New define_insn.\n\t(*mrgb + 1): New define_peephole2 pattern.\n\t(*mrgb + 2): New define_peephole2 pattern.\n\t* config/arc/arc.opt (mbitops): New option for nps400, uses\n\tTARGET_NPS400_BITOPS_DEFAULT.\n\t* config/arc/constraints.md (q): Make register class conditional.\n\t(Rrq): New register constraint.\n\t(Chs): New constraint.\n\t(Clo): New constraint.\n\t(Chi): New constraint.\n\t(Cbf): New constraint.\n\t(Cbn): New constraint.\n\t(C18): New constraint.\n\t(Cbi): New constraint.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/arc/extzv-1.c: New file.\n\t* gcc.target/arc/insv-1.c: New file.\n\t* gcc.target/arc/insv-2.c: New file.\n\t* gcc.target/arc/movb-1.c: New file.\n\t* gcc.target/arc/movb-2.c: New file.\n\t* gcc.target/arc/movb-3.c: New file.\n\t* gcc.target/arc/movb-4.c: New file.\n\t* gcc.target/arc/movb-5.c: New file.\n\t* gcc.target/arc/movb_cl-1.c: New file.\n\t* gcc.target/arc/movb_cl-2.c: New file.\n\t* gcc.target/arc/movbi_cl-1.c: New file.\n\t* gcc.target/arc/movl-1.c: New file.\n\t* gcc.target/arc/mrgb-1.c: New file.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/90a078f4c7d4a8caeacda49886443bcd23f5d25e"},{"sha":"944bac598a3deaabffaa9a5b199216b2cb551037","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: Mask integer 'L' operands to 32-bit\n\nWhen formatting 'L' operands (least significant word) only print\n32-bits, don't sign extend to 64-bits.\n\nThis commit could really be applied directly to the current GCC trunk,\nhowever, the only test I have for this issue right now relies on the\nnps400 bitops support.\n\ngcc/ChangeLog:\n\n\t* config/arc/arc.c (arc_print_operand): Print integer 'L' operands\n\tas 32-bits.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/arc/movh_cl-1.c: New file.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/944bac598a3deaabffaa9a5b199216b2cb551037"},{"sha":"fdd6b7afd52eef6df1b5a172c2f03d95df71bbab","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: Add an nps400 specific testcase\n\nThis test case triggered a bug caused by VOIDmode not being handled in\nproper_comparison_operator, this problem was fixed with a commit on\n2016-01-27 by Claudiu Zissulescu, adding this test case for coverage.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/arc/nps400-1.c: New file.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/fdd6b7afd52eef6df1b5a172c2f03d95df71bbab"},{"sha":"2f9e61275862654b5a051f65d4b258d273027b84","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"gcc/arc: Add __NPS400__ define for nps400 targets\n\nArrange to have the define __NPS400__ defined when compiling code for\nMellanox NPS400 ARC variant.\n\ngcc/ChangeLog:\n\n\t* conig/arc/arc.h (TARGET_CPU_CPP_BUILTINS): Add __NPS400__.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/2f9e61275862654b5a051f65d4b258d273027b84"},{"sha":"0557083520816b2570d390f65219d7b4a3b4291b","author":{"email":"9e1463dde329cd8931c832c7b15d6834477a4218@embecosm.com","name":"Joern Rennecke"},"message":"GLOBAL: fix gcc error which clobber reg\n\nTODO: Ideally I need to reproduce this bug and fill this in with a more\nin depth description of what is going wrong.\n\ngcc/ChangeLog:\n\n\t* reorg.c (reorg_set2live): New function.\n\t(reorg_redirect_jump): Use it.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/0557083520816b2570d390f65219d7b4a3b4291b"},{"sha":"ff9f43b51a151d44ac47d0e7e90eea681210a99b","author":{"email":"9e1463dde329cd8931c832c7b15d6834477a4218@embecosm.com","name":"Joern Rennecke"},"message":"GLOBAL: gcc: Some addresses can be considered constant\n\nTreat the addresses of global and static variables as constant when they\nare bound locally.\n\nThe thinking is that this change allows additional optimisation for\nEZchip, though there is a concern that this change may have negative\nside effects for other targets.  We need to carry out additional testing\nof this commit, or restructure it to be arc specific in some way.\n\ngcc/ChangeLog:\n\n\t* builtins.c (fold_builtin_constant_p): Consider addresses for\n\tglobal/static variables as constant when they are bound locally.\n\ngcc/testsuite/Change Log:\n\n\t* gcc.c-torture/execute/20130418-1.c: New test.\n\t* gcc.c-torture/execute/20130418-2.c: Likewise.\n\t* gcc.c-torture/execute/20130418-3.c: Likewise.\n\t* gcc.c-torture/execute/20130418-4.c: Likewise.\n\t* gcc.c-torture/execute/20130418-5.c: Likewise.\n\t* gcc.c-torture/execute/bcp-1.c (global): Initialise.\n\t(bad10): Moved to...\n\t(good3): ...here.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/ff9f43b51a151d44ac47d0e7e90eea681210a99b"},{"sha":"e68451c34b532813b037e549347764288e0d7b98","author":{"email":"73f46fa54e57e834aa9e13887532977467ddb664@embecosm.com","name":"Andrew Burgess"},"message":"GLOBAL: gcc: Allow code partitioning in more cases\n\nCurrently, placing a variable into a custom section results in the\nreorder-blocks-and-partition feature being deactivated.  This seems\nunnecessary, and the comments on the variable\nuser_defined_section_attribute (the mechanism by which the feature is\ndeactivated) suggests the deactivation should only have happened when a\nfunction is placed into a custom section.\n\nThis commit renames user_defined_section_attribute to\nfunc_with_user_defined_section_attribute to make its intended use a\nlittle clearer, and then ensures that the flag is only set when it is a\nfunction that has a custom section applied to it.\n\nThis change will aid targets that place data into custom sections, but\nleave code in the default section, and still wish to perform code\npartitioning.\n\ngcc/ChangeLog:\n\n\t* bb-reorder.c: Update comment on 'toplev.h' include.\n\t(pass_partition_blocks::gate): Update\n\tuser_defined_section_attribute to\n\tfunc_with_user_defined_section_attribute.\n\t* c-family/c-common.c (handle_section_attribute): Update\n\tuser_defined_section_attribute to\n\tfunc_with_user_defined_section_attribute.\n\t* final.c: Likewise.\n\t* toplev.c: Likewise.\n\t* toplev.h: Likewise.","distinct":true,"url":"https://api.github.com/repos/T-J-Teru/gcc/commits/e68451c34b532813b037e549347764288e0d7b98"}]}