{"action":"created","comment":{"url":"https://api.github.com/repos/trailofbits/mcsema/pulls/comments/91763599","pull_request_review_id":12275199,"id":91763599,"diff_hunk":"@@ -169,12 +169,144 @@ InstTransResult liftInstrImpl(InstPtr ip, BasicBlock *&block, NativeBlockPtr nb,\n     }\n   } else {\n     // Instruction translation not defined.\n-    errs() << \"Unsupported opcode \" << opcode << \"!\";\n+    errs() << \"Unsupported opcode \" << opcode << \" (\"\n+      << IP->getOpcodeName(opcode) << \"): \";\n     IP->printInst( &inst, errs(), to_string<VA>(ip->get_loc(), hex));\n-    // Print out the unhandled opcode.\n-    errs() << to_string<VA>(ip->get_loc(), hex) << \" \";\n-    errs() << strOut.str() << \"\\n\";\n-    errs() << inst.getOpcode() << \"\\n\";\n+    errs() << \"\\n\";\n+\n+    // In the case that we can't find the opcode, try building it out with","path":"mc-sema/cfgToLLVM/x86Instrs.cpp","position":14,"original_position":14,"commit_id":"ba0ee41b312b0e3731a783783f19365ef6104947","original_commit_id":"ba0ee41b312b0e3731a783783f19365ef6104947","user":{"login":"pgoodman","id":43664,"avatar_url":"https://avatars.githubusercontent.com/u/43664?v=3","gravatar_id":"","url":"https://api.github.com/users/pgoodman","html_url":"https://github.com/pgoodman","followers_url":"https://api.github.com/users/pgoodman/followers","following_url":"https://api.github.com/users/pgoodman/following{/other_user}","gists_url":"https://api.github.com/users/pgoodman/gists{/gist_id}","starred_url":"https://api.github.com/users/pgoodman/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/pgoodman/subscriptions","organizations_url":"https://api.github.com/users/pgoodman/orgs","repos_url":"https://api.github.com/users/pgoodman/repos","events_url":"https://api.github.com/users/pgoodman/events{/privacy}","received_events_url":"https://api.github.com/users/pgoodman/received_events","type":"User","site_admin":false},"body":"I'd like to see a comment here showing what the generated inline assembly looks like. What I am curious about is: can you splat actual disassembly into the inline asm block, then add a fixup prologue/epilogue that marshals the values to/from the register state structure. This *may* be what you're already doing, and if so, a comment in the code would illustrate that. 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instructions.","user":{"login":"jcranmer","id":589481,"avatar_url":"https://avatars.githubusercontent.com/u/589481?v=3","gravatar_id":"","url":"https://api.github.com/users/jcranmer","html_url":"https://github.com/jcranmer","followers_url":"https://api.github.com/users/jcranmer/followers","following_url":"https://api.github.com/users/jcranmer/following{/other_user}","gists_url":"https://api.github.com/users/jcranmer/gists{/gist_id}","starred_url":"https://api.github.com/users/jcranmer/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/jcranmer/subscriptions","organizations_url":"https://api.github.com/users/jcranmer/orgs","repos_url":"https://api.github.com/users/jcranmer/repos","events_url":"https://api.github.com/users/jcranmer/events{/privacy}","received_events_url":"https://api.github.com/users/jcranmer/received_events","type":"User","site_admin":false},"body":"This won't support all cases (256-bit and 512-bit instructions for sure), but\r\nthis should allow for correctness on unknown instructions, even if the generated\r\noutput will cause the optimizers to throw their hands up in the air.\r\n\r\nI tested this out using AESNI instructions because I can't imagine anyone taking the time to actually write the tables for these to raise them to intrinsics.\r\n\r\nFWIW, the use of template parameters for R_READ/R_WRITE as opposed to a parameter made this much harder than it had to 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