{"action":"created","issue":{"url":"https://api.github.com/repos/riscv/riscv-pk/issues/43","repository_url":"https://api.github.com/repos/riscv/riscv-pk","labels_url":"https://api.github.com/repos/riscv/riscv-pk/issues/43/labels{/name}","comments_url":"https://api.github.com/repos/riscv/riscv-pk/issues/43/comments","events_url":"https://api.github.com/repos/riscv/riscv-pk/issues/43/events","html_url":"https://github.com/riscv/riscv-pk/issues/43","id":194376156,"number":43,"title":"bbl always access \"Invalid htif register address\"","user":{"login":"shrshore","id":12680986,"avatar_url":"https://avatars.githubusercontent.com/u/12680986?v=3","gravatar_id":"","url":"https://api.github.com/users/shrshore","html_url":"https://github.com/shrshore","followers_url":"https://api.github.com/users/shrshore/followers","following_url":"https://api.github.com/users/shrshore/following{/other_user}","gists_url":"https://api.github.com/users/shrshore/gists{/gist_id}","starred_url":"https://api.github.com/users/shrshore/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/shrshore/subscriptions","organizations_url":"https://api.github.com/users/shrshore/orgs","repos_url":"https://api.github.com/users/shrshore/repos","events_url":"https://api.github.com/users/shrshore/events{/privacy}","received_events_url":"https://api.github.com/users/shrshore/received_events","type":"User","site_admin":false},"labels":[],"state":"open","locked":false,"assignee":null,"assignees":[],"milestone":null,"comments":2,"created_at":"2016-12-08T16:09:25Z","updated_at":"2016-12-14T16:22:48Z","closed_at":null,"body":"when I build this project to boot the 32-bit linux kernel with bbl, it always print out that “Invalid htif register address\" and exit.\r\nHere is my configuration of riscv-pk:\r\n```\r\n$ cd riscv-pk\r\n$ mkdir build\r\n$ cd build\r\n$ ../configure --prefix=$RISCV --host=riscv32-unknown-linux-gnu --enable-32bit --with-payload=/home/shore/linux-4.6.2/vmlinux\r\n$ make\r\n$ make install\r\n```\r\nAnd when I run the bbl with payload of RV32 linux kernel on qemu \r\n```\r\n$ cd ../riscv-qemu\r\n$ ./riscv32-softmmu/qemu-system-riscv32 -nographic -kernel /home/shore/riscv/riscv32-unknown-elf/bin/bbl\r\n```\r\nI wonder how to fix this error to boot the linux kernel. Anyone can help?"},"comment":{"url":"https://api.github.com/repos/riscv/riscv-pk/issues/comments/267079358","html_url":"https://github.com/riscv/riscv-pk/issues/43#issuecomment-267079358","issue_url":"https://api.github.com/repos/riscv/riscv-pk/issues/43","id":267079358,"user":{"login":"sorear","id":92735,"avatar_url":"https://avatars.githubusercontent.com/u/92735?v=3","gravatar_id":"","url":"https://api.github.com/users/sorear","html_url":"https://github.com/sorear","followers_url":"https://api.github.com/users/sorear/followers","following_url":"https://api.github.com/users/sorear/following{/other_user}","gists_url":"https://api.github.com/users/sorear/gists{/gist_id}","starred_url":"https://api.github.com/users/sorear/starred{/owner}{/repo}","subscriptions_url":"https://api.github.com/users/sorear/subscriptions","organizations_url":"https://api.github.com/users/sorear/orgs","repos_url":"https://api.github.com/users/sorear/repos","events_url":"https://api.github.com/users/sorear/events{/privacy}","received_events_url":"https://api.github.com/users/sorear/received_events","type":"User","site_admin":false},"created_at":"2016-12-14T16:22:48Z","updated_at":"2016-12-14T16:22:48Z","body":"Actually riscv-qemu doesn't seem to even build right now in a 32-bit chroot: @sagark \r\n\r\n```\r\n/home/test/riscv-qemu/hw/riscv/sifive_board.c:215:5: error: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'uint64_t' [-Werror=format=]\r\n     sprintf(ramsize_as_hex_str, \"%016lx\", rsz);\r\n```\r\n\r\n@shrshore If you have a patch that fixes the build in a non-hacky way, that would be useful to discuss as a PR against qemu."}}
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