{"push_id":1247081776,"size":71,"distinct_size":71,"ref":"refs/heads/master2","head":"ccd675519af626b6705f8a6dea66f10b3643de39","before":"b172de8046d1bf66e959155eca032a8f48b7f47f","commits":[{"sha":"cfc6351aa5d43fd6e5853414d0dc61b72be61884","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"fs: don't export symbol get_write_access\n\nIt's declared static anyway.","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/cfc6351aa5d43fd6e5853414d0dc61b72be61884"},{"sha":"71c5e694b24010c80e74a8aa6646569626657bef","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"scripts: tune XZ for ARM\n\nI'm puzzled by depth=65.  Values between 50 and 75 compress more\nefficiently than anything else.","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/71c5e694b24010c80e74a8aa6646569626657bef"},{"sha":"60415f3f5e4769be8eacb8535090310b5a338c69","author":{"name":"Andi Kleen","email":"c11846b976c384ad30536475c5d4d3ae71259b65@linux.intel.com"},"message":"mutex: use asmlinkage properly\n\nVarious kernel/mutex.c functions can be called from\ninline assembler, so they should be all global asmlinkage.\n\nThis also allows dropping some __useds\n\nSigned-off-by: Andi Kleen <ak@linux.intel.com>","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/60415f3f5e4769be8eacb8535090310b5a338c69"},{"sha":"8cca65dde0ac284400040ba0ab6db9bd28ef7b5d","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"Mark a few hot functions as such","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/8cca65dde0ac284400040ba0ab6db9bd28ef7b5d"},{"sha":"c9a78f3db5e7890080f8b958ad6062c947bd8535","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"Export dump_stack in generic code, not arch-specific","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/c9a78f3db5e7890080f8b958ad6062c947bd8535"},{"sha":"c2f2f832e5003c6c010a117977d2d7d25a3dd551","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"Disable block device entropy gathering","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/c2f2f832e5003c6c010a117977d2d7d25a3dd551"},{"sha":"45ce917c5ba4cdb6e2d0cdf00fcbe3362230d0a9","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"Fix tons of new warnings from GCC5","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/45ce917c5ba4cdb6e2d0cdf00fcbe3362230d0a9"},{"sha":"f64c5dc5d4105080e330c53bf9502db2f077a21f","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"arm: clean up atomics","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/f64c5dc5d4105080e330c53bf9502db2f077a21f"},{"sha":"ba8e767ae4bb9c4feece8f2ccbf2ab47515a855d","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"ARM: bitops: prefetch the destination word for write prior to strex\n\nThe cost of changing a cacheline from shared to exclusive state can be\nsignificant, especially when this is triggered by an exclusive store,\nsince it may result in having to retry the transaction.\n\nThis patch prefixes our atomic bitops implementation with prefetchw,\nto try and grab the line in exclusive state from the start. The testop\nmacro is left alone, since the barrier semantics limit the usefulness\nof prefetching data.\n\nAcked-by: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\n\nARM: 7907/1: lib: delay-loop: Add align directive to fix BogoMIPS calculation\n\nCurrently mx53 (CortexA8) running at 1GHz reports:\nCalibrating delay loop... 663.55 BogoMIPS (lpj=3317760)\n\nTom Evans verified that alignments of 0x0 and 0x8 run the two instructions of __loop_delay in one clock cycle (1 clock/loop), while alignments of 0x4 and 0xc take 3 clocks to run the loop twice. (1.5 clock/loop)\n\nThe original object code looks like this:\n\n00000010 <__loop_const_udelay>:\n  10:\te3e01000 \tmvn\tr1, #0\n  14:\te51f201c \tldr\tr2, [pc, #-28]\t; 0 <__loop_udelay-0x8>\n  18:\te5922000 \tldr\tr2, [r2]\n  1c:\te0800921 \tadd\tr0, r0, r1, lsr #18\n  20:\te1a00720 \tlsr\tr0, r0, #14\n  24:\te0822b21 \tadd\tr2, r2, r1, lsr #22\n  28:\te1a02522 \tlsr\tr2, r2, #10\n  2c:\te0000092 \tmul\tr0, r2, r0\n  30:\te0800d21 \tadd\tr0, r0, r1, lsr #26\n  34:\te1b00320 \tlsrs\tr0, r0, #6\n  38:\t01a0f00e \tmoveq\tpc, lr\n\n0000003c <__loop_delay>:\n  3c:\te2500001 \tsubs\tr0, r0, #1\n  40:\t8afffffe \tbhi\t3c <__loop_delay>\n  44:\te1a0f00e \tmov\tpc, lr\n\nAfter adding the 'align 3' directive to __loop_delay (align to 8 bytes):\n\n00000010 <__loop_const_udelay>:\n  10:\te3e01000 \tmvn\tr1, #0\n  14:\te51f201c \tldr\tr2, [pc, #-28]\t; 0 <__loop_udelay-0x8>\n  18:\te5922000 \tldr\tr2, [r2]\n  1c:\te0800921 \tadd\tr0, r0, r1, lsr #18\n  20:\te1a00720 \tlsr\tr0, r0, #14\n  24:\te0822b21 \tadd\tr2, r2, r1, lsr #22\n  28:\te1a02522 \tlsr\tr2, r2, #10\n  2c:\te0000092 \tmul\tr0, r2, r0\n  30:\te0800d21 \tadd\tr0, r0, r1, lsr #26\n  34:\te1b00320 \tlsrs\tr0, r0, #6\n  38:\t01a0f00e \tmoveq\tpc, lr\n  3c:\te320f000 \tnop\t{0}\n\n00000040 <__loop_delay>:\n  40:\te2500001 \tsubs\tr0, r0, #1\n  44:\t8afffffe \tbhi\t40 <__loop_delay>\n  48:\te1a0f00e \tmov\tpc, lr\n  4c:\te320f000 \tnop\t{0}\n\n, which now reports:\nCalibrating delay loop... 996.14 BogoMIPS (lpj=4980736)\n\nSome more test results:\n\nOn mx31 (ARM1136) running at 532 MHz, before the patch:\nCalibrating delay loop... 351.43 BogoMIPS (lpj=1757184)\n\nOn mx31 (ARM1136) running at 532 MHz after the patch:\nCalibrating delay loop... 528.79 BogoMIPS (lpj=2643968)\n\nAlso tested on mx6 (CortexA9) and on mx27 (ARM926), which shows the same\nBogoMIPS value before and after this patch.\n\nReported-by: Tom Evans <tom_usenet@optusnet.com.au>\nSuggested-by: Tom Evans <tom_usenet@optusnet.com.au>\nSigned-off-by: Fabio Estevam <fabio.estevam@freescale.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nARM: 7404/1: cmpxchg64: use atomic64 and local64 routines for cmpxchg64\n\nThe cmpxchg64 routines for ARMv6+ CPUs replicate inline assembly that\nalready exists for atomic64 operations. Furthermore, the cmpxchg64 code\nuses the \"memory\" constraint in the clobber list rather than identifying\nthe region of memory that is actually modified.\n\nThis patch replaces the ARMv6+ cmpxchg64 code with macros that expand to\nthe atomic64_ and local64_ variants, casting the pointer parameter to\nthe appropriate container type.\n\nCc: Nicolas Pitre <nico@linaro.org>\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nARM: 7720/1: ARM v6/v7 cmpxchg64 shouldn't clear upper 32 bits of the old/new value\n\nThe implementation of cmpxchg64() for the ARM v6 and v7 architecture\ncasts parameter 2 and 3 (the old and new 64bit values) to an unsigned\nlong before calling the atomic_cmpxchg64() function. This clears\nthe top 32 bits of the old and new values, resulting in the wrong\nvalues being compare-exchanged. Luckily, this only appears to be used\nfor 64-bit sched_clock, which we don't (yet) have on ARM.\n\nThis bug was introduced by commit 3e0f5a15f500 (\"ARM: 7404/1: cmpxchg64:\nuse atomic64 and local64 routines for cmpxchg64\").\n\nCc: <stable@vger.kernel.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nARM: 7852/1: cmpxchg: implement barrier-less cmpxchg64_local\n\nOur cmpxchg64 macros are wrappers around atomic64_cmpxchg. Whilst this is\ngreat for code re-use, there is a case for barrier-less cmpxchg where it\nis known to be safe (for example cmpxchg64_local and cmpxchg-based\nlockrefs).\n\nThis patch introduces a 64-bit cmpxchg implementation specifically\nfor the cmpxchg64_* macros, so that it can be later used by the lockref\ncode.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nARM: 7853/1: cmpxchg: implement cmpxchg64_relaxed\n\nThis patch introduces cmpxchg64_relaxed for arm, which performs a 64-bit\ncmpxchg operation without barrier semantics. cmpxchg64_local is updated\nto use the new operation.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>\n\nARM: 7984/1: prefetch: add prefetchw invocations for barriered atomics\n\nAfter a bunch of benchmarking on the interaction between dmb and pldw,\nit turns out that issuing the pldw *after* the dmb instruction can\ngive modest performance gains (~3% atomic_add_return improvement on a\ndual A15).\n\nThis patch adds prefetchw invocations to our barriered atomic operations\nincluding cmpxchg, test_and_xxx and futexes.\n\nChange-Id: Id6ebfe82ff9578c27e2b745e2cce167200112606\nSigned-off-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Russell King <rmk+kernel@arm.linux.org.uk>","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/ba8e767ae4bb9c4feece8f2ccbf2ab47515a855d"},{"sha":"f059961eae7644282eee5e5e72122b6c05c2f92b","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"arm: prefetch before atomic_add/_sub","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/f059961eae7644282eee5e5e72122b6c05c2f92b"},{"sha":"b11d38cb29ac1e0b82cfa3b75f40161fe1a95e14","author":{"name":"Ryan Pennucci","email":"a333f4d08fae2e33abcef101df74db68510c12d6@gmail.com"},"message":"arm: fix atomic_set_mask","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/b11d38cb29ac1e0b82cfa3b75f40161fe1a95e14"},{"sha":"17ae5f017edcbe02ba49dbe865bf00a82d3810d6","author":{"name":"H. Peter Anvin","email":"2dad3f7077c675f93d9f139c5cc03297031ec6b0@zytor.com"},"message":"kernel: Replace timeconst.pl with a bc script\n\nbc is the standard tool for multi-precision arithmetic.  We switched\nto Perl because akpm reported a hard-to-reproduce build hang, which\nwas very odd because affected and unaffected machines were all running\nthe same version of GNU bc.\n\nUnfortunately switching to Perl required a really ugly \"canning\"\nmechanism to support Perl < 5.8 installations lacking the Math::BigInt\nmodule.\n\nIt was recently pointed out to me that some very old versions of GNU\nmake had problems with pipes in subshells, which was indeed the\nconstruct used in the Makefile rules in that version of the patch;\nPerl didn't need it so switching to Perl fixed the problem for\nunrelated reasons.  With the problem (hopefully) root-caused, we can\nswitch back to bc and do the arbitrary-precision arithmetic naturally.\n\nSigned-off-by: H. Peter Anvin <hpa@zytor.com>\nCc: Andrew Morton <akpm@linux-foundation.org>\nAcked-by: Sam Ravnborg <sam@ravnborg.org>\nSigned-off-by: Michal Marek <mmarek@suse.cz>\n\nChange-Id: I8450a919c2d27b6c18561621c0a48a762e46a22d","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/17ae5f017edcbe02ba49dbe865bf00a82d3810d6"},{"sha":"a2df398fb68e4c971aec024a74a2d18351e00d98","author":{"name":"Rusty Russell","email":"69f5932eb9977dcad4aeec4104f9f99d5dd1ae66@rustcorp.com.au"},"message":"kernel/hz.bc: ignore.\n\nChange-Id: I96e5465162eec64287b715b5e0df726a2636194d\nSigned-off-by: Rusty Russell <rusty@rustcorp.com.au>\nSigned-off-by: Linus Torvalds <torvalds@linux-foundation.org>\n(cherry picked from commit eed6bc8ec8f31dd5f4d68eabf47376763f8d1f20)","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/a2df398fb68e4c971aec024a74a2d18351e00d98"},{"sha":"052e1849fe76803a746dc56ff1474945e259886a","author":{"name":"Stepan Moskovchenko","email":"3ac2ffba2042866ba69d055bf2d86c77dcba309b@codeaurora.org"},"message":"ARM: Use -mcpu=cortex-a15 when targeting MSM Krait CPUs\n\nEnable compiler optimizations specific to the Cortex-A15\nprocessor when targeting MSM Krait CPUs. This is necessary\ntake advantage of the UDIV/SDIV instructions supported by\nthese processors. To accomplish this, we need to remove the\n-march=armv7-a ISA restriction from the compiler options\nbecause 'cortex-a15' is a superset of 'armv7-a'.\n\nChange-Id: I6215aecc11fb4f77c971de7b84f68649ef234357\nSigned-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>\nSigned-off-by: flar2 <asegaert@gmail.com>","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/052e1849fe76803a746dc56ff1474945e259886a"},{"sha":"2cf8ab7cdae21f0792cd48aa0db51b2f0b8e55d6","author":{"name":"Jake Weinstein","email":"6dccd8142a7a8a265024f1df602d29c11823a71c@gmail.com"},"message":"ARM: enable hard float and set A15 flags\n\nChange-Id: Ia9c46307c5a73c5aa1c80fffefe8b245ab8e0687","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/2cf8ab7cdae21f0792cd48aa0db51b2f0b8e55d6"},{"sha":"2575309ffb28333848d28626aa9ae1208d051358","author":{"name":"Jake Weinstein","email":"6dccd8142a7a8a265024f1df602d29c11823a71c@gmail.com"},"message":"ARM: enable -pipe flag","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/2575309ffb28333848d28626aa9ae1208d051358"},{"sha":"38728f5b8dea82c0782adaed5b4797b7f9830c57","author":{"name":"pattyboi","email":"18935c780f5583c5596a599b28035c89e483cc75@gmail.com"},"message":"finish up compiler flags.","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/38728f5b8dea82c0782adaed5b4797b7f9830c57"},{"sha":"c8e1722028d323b8e70f7a2754c4452cb6a330a2","author":{"name":"pattyboi","email":"18935c780f5583c5596a599b28035c89e483cc75@gmail.com"},"message":"set intial cpu speeds,","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/c8e1722028d323b8e70f7a2754c4452cb6a330a2"},{"sha":"4f30088ca7b352624e8f766b4703b9ae41783a73","author":{"name":"Riley Andrews","email":"ec394072c869ae2f7d03d8e22257cb0e3246a0c6@google.com"},"message":"cpuidle: Add nop idle governor.\n\nThe lpm cpuidle driver does all its idle state calculations\nin the driver, as opposed to in the governor. To avoid pointless\nwork, add a null cpuidle governor that returns fixed idle\nstate to move to, the result of which can be ignored.\n\nChange-Id: I7e29513126e91023af13794792235bc4b5500d06\nSigned-off-by: Riley Andrews <riandrews@google.com>","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/4f30088ca7b352624e8f766b4703b9ae41783a73"},{"sha":"a2752f806595e18629c9f5256f2cf65e14f1a8a4","author":{"name":"morfic","email":"24c91174af5e75ff304600d4e98b9fb8de7c6030@gmail.com"},"message":"Let's nuke the wrapper early this time.","distinct":true,"url":"https://api.github.com/repos/pattyboi/msm/commits/a2752f806595e18629c9f5256f2cf65e14f1a8a4"}]}
{"actor":{"display_login":"pattyboi"}}