{"push_id":1055819048,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"5f51ad4ac26541bcde0bad49d168b6f32ee40295","before":"538a39851795378e8ee6440ee0ebe2ac901e8eaa","commits":[{"sha":"5f51ad4ac26541bcde0bad49d168b6f32ee40295","author":{"email":"6908004fa6eaed11091185c2620eb722860dc825@amd.com","name":"Valery Pykhtin"},"message":"[AMDGPU] fix readlane/readfirstlane src vgpr operand type.\n\nFor VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand).\nreadfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).\n\nDifferential Revision: http://reviews.llvm.org/D18696","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project/commits/5f51ad4ac26541bcde0bad49d168b6f32ee40295"}]}