{"push_id":1412053433,"size":1,"distinct_size":1,"ref":"refs/heads/master","head":"228513a4aa86db41006de3d3c15328ea4c99222c","before":"e9a5f9453bd8b8007dc40ed77188bdb30575b621","commits":[{"sha":"228513a4aa86db41006de3d3c15328ea4c99222c","author":{"name":"Daniel Sanders","email":"11d7e2af1a379271955e5fef131dc5a28fc141a8@apple.com"},"message":"Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.\n\nSummary:\n* ARM is omitted from this patch because this check appears to expose bugs in this target.\n* Mips is omitted from this patch because this check either detects bugs or deliberate\n  emission of instructions that don't satisfy their predicates. One deliberate\n  use is the SYNC instruction where the version with an operand is correctly\n  defined as requiring MIPS32 while the version without an operand is defined\n  as an alias of 'SYNC 0' and requires MIPS2.\n* X86 is omitted from this patch because it doesn't use the tablegen-erated\n  MCCodeEmitter infrastructure.\n\nPatches for ARM and Mips will follow.\n\nDepends on D25617\n\nReviewers: tstellarAMD, jmolloy\n\nSubscribers: wdng, jmolloy, aemerson, rengolin, arsenm, jyknight, nemanjai, nhaehnle, tstellarAMD, llvm-commits\n\nDifferential Revision: https://reviews.llvm.org/D25618","distinct":true,"url":"https://api.github.com/repos/llvm-project/llvm-project-submodule/commits/228513a4aa86db41006de3d3c15328ea4c99222c"}]}
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