{"push_id":1143929917,"size":35,"distinct_size":0,"ref":"refs/heads/caf/torvalds/master","head":"8c52b6dcdd1994ad0d2672e43c8d975d5c8195c3","before":"4340fa55298d17049e71c7a34e04647379c269f3","commits":[{"sha":"59fa5860204ffc95128d60cba9f54f9740a42c7d","author":{"name":"Matt Redfearn","email":"c5b62b631b0bb11c9c59278f295d5b8e1a4873c6@imgtec.com"},"message":"genirq: Fix missing return value in irq_destroy_ipi()\n\nCommit 7cec18a3906b changed the return type of irq_destroy_ipi to int, but\nmissed adding a value to one return statement. Fix this to silence the\nresulting compiler warning:\n\nkernel/irq/ipi.c In function ‘irq_destroy_ipi’:\nkernel/irq/ipi.c:128:3: warning: ‘return’ with no value, in function returning non-void [-Wreturn-type]\n\nFixes: 7cec18a3906b \"genirq: Add error code reporting to irq_{reserve,destroy}_ipi\"\nSigned-off-by: Matt Redfearn <matt.redfearn@imgtec.com>\nCc: linux-mips@linux-mips.org\nLink: http://lkml.kernel.org/r/1464086550-24734-1-git-send-email-matt.redfearn@imgtec.com\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/59fa5860204ffc95128d60cba9f54f9740a42c7d"},{"sha":"871e178e0f2c4fa788f694721a10b4758d494ce1","author":{"name":"Russell Currey","email":"2eacafec92f559d51886f12bbdf842327b6af83e@russell.cc"},"message":"powerpc/pseries/eeh: Handle RTAS delay requests in configure_bridge\n\nIn the \"ibm,configure-pe\" and \"ibm,configure-bridge\" RTAS calls, the\nspec states that values of 9900-9905 can be returned, indicating that\nsoftware should delay for 10^x (where x is the last digit, i.e. 990x)\nmilliseconds and attempt the call again. Currently, the kernel doesn't\nknow about this, and respecting it fixes some PCI failures when the\nhypervisor is busy.\n\nThe delay is capped at 0.2 seconds.\n\nCc: <stable@vger.kernel.org> # 3.10+\nSigned-off-by: Russell Currey <ruscur@russell.cc>\nAcked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/871e178e0f2c4fa788f694721a10b4758d494ce1"},{"sha":"bd000b82e86503d5e8b9e6d40a3257bc9dddb96d","author":{"name":"Russell Currey","email":"2eacafec92f559d51886f12bbdf842327b6af83e@russell.cc"},"message":"powerpc/pseries/eeh: Refactor the configure_bridge RTAS tokens\n\nThe RTAS calls \"ibm,configure-pe\" and \"ibm,configure-bridge\" perform the\nsame actions, however the former can skip configuration if unnecessary.\nThe existing code treats them as different tokens even though only one\nwill ever be called.  Refactor this by making a single token that is\nassigned during init.\n\nSigned-off-by: Russell Currey <ruscur@russell.cc>\nAcked-by: Gavin Shan <gwshan@linux.vnet.ibm.com>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/bd000b82e86503d5e8b9e6d40a3257bc9dddb96d"},{"sha":"ab2e1b89230fa80328262c91d2d0a539a2790d6f","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"Revert \"arm64: hugetlb: partial revert of 66b3923a1a0f\"\n\nThis reverts commit ff7925848b50050732ac0401e0acf27e8b241d7b.\n\nNow that the contiguous-hint hugetlb regression has been debugged and\nfixed upstream by 66ee95d16a7f (\"mm: exclude HugeTLB pages from THP\npage_mapped() logic\"), we can revert the previous partial revert of this\nfeature.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/ab2e1b89230fa80328262c91d2d0a539a2790d6f"},{"sha":"d23fac2b27d94aeb7b65536a50d32bfdc21fe01e","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"powerpc: Fix definition of SIAR and SDAR registers\n\nThe SIAR and SDAR registers are available twice, one time as SPRs\n780 / 781 (unprivileged, but read-only), and one time as the SPRs\n796 / 797 (privileged, but read and write). The Linux kernel code\ncurrently uses the unprivileged  SPRs - while this is OK for reading,\nwriting to that register of course does not work.\nSince the KVM code tries to write to this register, too (see the mtspr\nin book3s_hv_rmhandlers.S), the contents of this register sometimes get\nlost for the guests, e.g. during migration of a VM.\nTo fix this issue, simply switch to the privileged SPR numbers instead.\n\nCc: stable@vger.kernel.org\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nAcked-by: Paul Mackerras <paulus@ozlabs.org>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/d23fac2b27d94aeb7b65536a50d32bfdc21fe01e"},{"sha":"8dd75ccb571f3c92c48014b3dabd3d51a115ab41","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"powerpc: Use privileged SPR number for MMCR2\n\nWe are already using the privileged versions of MMCR0, MMCR1\nand MMCRA in the kernel, so for MMCR2, we should better use\nthe privileged versions, too, to be consistent.\n\nFixes: 240686c13687 (\"powerpc: Initialise PMU related regs on Power8\")\nCc: stable@vger.kernel.org # v3.10+\nSuggested-by: Paul Mackerras <paulus@ozlabs.org>\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nAcked-by: Paul Mackerras <paulus@ozlabs.org>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/8dd75ccb571f3c92c48014b3dabd3d51a115ab41"},{"sha":"db413b51c0d023b336634ffbf5eb29128245df8d","author":{"name":"Robin Murphy","email":"74ee054f2911f160e9f54bee1a41a27f813ebb5a@arm.com"},"message":"arm64: Remove orphaned __addr_ok() definition\n\nSince commit 12a0ef7b0ac3 (\"arm64: use generic strnlen_user and\nstrncpy_from_user functions\"), the definition of __addr_ok() has been\nlanguishing unused; eradicate the sucker.\n\nCC: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Robin Murphy <robin.murphy@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/db413b51c0d023b336634ffbf5eb29128245df8d"},{"sha":"604c8e676e609da9f17a2abb36f2b2067bb86561","author":{"name":"Mark Rutland","email":"7bbc68f29a82fb2eb4daac9d4df0c3f473a4ef26@arm.com"},"message":"arm64: enable CONFIG_SET_MODULE_RONX by default\n\nThe SET_MODULE_RONX protections are effectively the same as the\nDEBUG_RODATA protections we enabled by default back in commit\n57efac2f7108e325 (\"arm64: enable CONFIG_DEBUG_RODATA by default\"). It\nseems unusual to have one but not the other.\n\nAs evidenced by the help text, the rationale appears to be that\nSET_MODULE_RONX interacts poorly with tracing and patching, but both of\nthese make use of the insn framework, which takes SET_MODULE_RONX into\naccount. Any remaining issues are bugs which should be fixed regardless\nof the default state of the option.\n\nThis patch enables DEBUG_SET_MODULE_RONX by default, and replaces the\nhelp text with a new wording derived from the DEBUG_RODATA help text,\nwhich better describes the functionality. Previously, the DEBUG_RODATA\nentry was inconsistently indented with spaces, which are replaced with\ntabs as with the other Kconfig entries.\n\nAdditionally, the wording of recommended defaults is made consistent for\nall options. These are placed in a new paragraph, unquoted, as a full\nsentence (with a period/full stop) as this appears to be the most common\nform per $(git grep 'in doubt').\n\nCc: Catalin Marinas <catalin.marinas@arm.com>\nCc: Laura Abbott <labbott@fedoraproject.org>\nAcked-by: Kees Cook <keescook@chromium.org>\nAcked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\nSigned-off-by: Mark Rutland <mark.rutland@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/604c8e676e609da9f17a2abb36f2b2067bb86561"},{"sha":"e47b020a323d1b2a7b1e9aac86e99eae19463630","author":{"name":"Catalin Marinas","email":"6aa257b0f6444d48b36b727fdf3f5c1074b85fd0@arm.com"},"message":"arm64: Provide \"model name\" in /proc/cpuinfo for PER_LINUX32 tasks\n\nThis patch brings the PER_LINUX32 /proc/cpuinfo format more in line with\nthe 32-bit ARM one by providing an additional line:\n\nmodel name      : ARMv8 Processor rev X (v8l)\n\nCc: <stable@vger.kernel.org>\nAcked-by: Will Deacon <will.deacon@arm.com>\nSigned-off-by: Catalin Marinas <catalin.marinas@arm.com>\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/e47b020a323d1b2a7b1e9aac86e99eae19463630"},{"sha":"d6c886006c948141f24e84acebfb757d3200f20c","author":{"name":"Aneesh Kumar K.V","email":"e35455d9785cc3190a5bd1427d7474d5511fd373@linux.vnet.ibm.com"},"message":"powerpc/mm/radix: Update LPCR only if it is powernv\n\nLPCR cannot be updated when running in guest mode.\n\nFixes: 2bfd65e45e87 (\"powerpc/mm/radix: Add radix callbacks for early init routines\")\nSigned-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/d6c886006c948141f24e84acebfb757d3200f20c"},{"sha":"dc47c0c1f8099fccb2c1e2f3775855066a9e4484","author":{"name":"Aneesh Kumar K.V","email":"e35455d9785cc3190a5bd1427d7474d5511fd373@linux.vnet.ibm.com"},"message":"powerpc/mm/hash: Fix the reference bit update when handling hash fault\n\nWhen we converted the asm routines to C functions, we missed updating\nHPTE_R_R based on _PAGE_ACCESSED. ASM code used to copy over the lower\nbits from pte via.\n\nandi.\tr3,r30,0x1fe\t\t/* Get basic set of flags */\n\nWe also update the code such that we won't update the Change bit ('C'\nbit) always. This was added by commit c5cf0e30bf3d8 (\"powerpc: Fix\nbuglet with MMU hash management\").\n\nWith hash64, we need to make sure that hardware doesn't do a pte update\ndirectly. This is because we do end up with entries in TLB with no hash\npage table entry. This happens because when we find a hash bucket full,\nwe \"evict\" a more/less random entry from it. When we do that we don't\ninvalidate the TLB (hpte_remove) because we assume the old translation\nis still technically \"valid\". For more info look at commit\n0608d692463(\"powerpc/mm: Always invalidate tlb on hpte invalidate and\nupdate\").\n\nThus it's critical that valid hash PTEs always have reference bit set\nand writeable ones have change bit set. We do this by hashing a\nnon-dirty linux PTE as read-only and always setting _PAGE_ACCESSED (and\nthus R) when hashing anything else in. Any attempt by Linux at clearing\nthose bits also removes the corresponding hash entry.\n\nCommit 5cf0e30bf3d8 did that for 'C' bit by enabling 'C' bit always.\nWe don't really need to do that because we never map a RW pte entry\nwithout setting 'C' bit. On READ fault on a RW pte entry, we still map\nit READ only, hence a store update in the page will still cause a hash\npte fault.\n\nThis patch reverts the part of commit c5cf0e30bf3d8 (\"[PATCH] powerpc:\nFix buglet with MMU hash management\") and retain the updatepp part.\n\n- If we hit the updatepp path on native, the old code without that\n  commit, would fail to set C bcause native_hpte_updatepp()\n  was implemented to filter the same bits as H_PROTECT and not let C\n  through thus we would \"upgrade\" a RO HPTE to RW without setting C\n  thus causing the bug. So the real fix in that commit was the change\n  to native_hpte_updatepp\n\nFixes: 89ff725051d1 (\"powerpc/mm: Convert __hash_page_64K to C\")\nCc: stable@vger.kernel.org # v4.5+\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nSigned-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/dc47c0c1f8099fccb2c1e2f3775855066a9e4484"},{"sha":"157d4d0620879b7d89ca1e3cd7bf0be1e29be198","author":{"name":"Aneesh Kumar K.V","email":"e35455d9785cc3190a5bd1427d7474d5511fd373@linux.vnet.ibm.com"},"message":"powerpc/mm/radix: Add missing tlb flush\n\nThis should not have any impact on hash, because hash does tlb\ninvalidate with every pte update and we don't implement\nflush_tlb_* functions for hash. With radix we should make an explicit\ncall to flush tlb outside pte update.\n\nSigned-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/157d4d0620879b7d89ca1e3cd7bf0be1e29be198"},{"sha":"7cc851039d643a2ee7df4d18177150f2c3a484f5","author":{"name":"Thomas Huth","email":"88e8c2c9848c27f046284b2ccf48cd5b58fafc02@redhat.com"},"message":"powerpc/pseries: Add POWER8NVL support to ibm,client-architecture-support call\n\nIf we do not provide the PVR for POWER8NVL, a guest on this system\ncurrently ends up in PowerISA 2.06 compatibility mode on KVM, since QEMU\ndoes not provide a generic PowerISA 2.07 mode yet. So some new\ninstructions from POWER8 (like \"mtvsrd\") get disabled for the guest,\nresulting in crashes when using code compiled explicitly for\nPOWER8 (e.g. with the \"-mcpu=power8\" option of GCC).\n\nFixes: ddee09c099c3 (\"powerpc: Add PVR for POWER8NVL processor\")\nCc: stable@vger.kernel.org # v4.0+\nSigned-off-by: Thomas Huth <thuth@redhat.com>\nSigned-off-by: Michael Ellerman <mpe@ellerman.id.au>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/7cc851039d643a2ee7df4d18177150f2c3a484f5"},{"sha":"10fdf8513f776c8b2588bb7b924fb243ae2462d6","author":{"name":"Will Deacon","email":"b2e33b86f3f248a395aadfb8ef1908ac314f4233@arm.com"},"message":"arm64: unistd32.h: wire up missing syscalls for compat tasks\n\nWe're missing entries for mlock2, copy_file_range, preadv2 and pwritev2\nin our compat syscall table, so hook them up. Only the last two need\ncompat wrappers.\n\nSigned-off-by: Will Deacon <will.deacon@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/10fdf8513f776c8b2588bb7b924fb243ae2462d6"},{"sha":"dfc2507b26af22b0bbc85251b8545b36d8bc5d72","author":{"name":"John Stultz","email":"43a1884c0f1dca3e1332089eeb4ce74424519f3b@linaro.org"},"message":"time: Make settimeofday error checking work again\n\nIn commit 86d3473224b0 some of the checking for a valid timeval\nwas subtley changed which caused -EINVAL to be returned whenever\nthe timeval was null.\n\nHowever, it is possible to set the timezone data while specifying\na NULL timeval, which is usually done to handle systems where the\nRTC keeps local time instead of UTC. Thus the patch causes such\nsystems to have the time incorrectly set.\n\nThis patch addresses the issue by handling the error conditionals\nin the same way as was done previously.\n\nFixes: 86d3473224b0 \"time: Introduce do_sys_settimeofday64()\"\nReported-by: Mika Westerberg <mika.westerberg@linux.intel.com>\nSigned-off-by: John Stultz <john.stultz@linaro.org>\nTested-by: Mika Westerberg <mika.westerberg@linux.intel.com>\nCc: Prarit Bhargava <prarit@redhat.com>\nCc: Arnd Bergmann <arnd@arndb.de>\nCc: Baolin Wang <baolin.wang@linaro.org>\nCc: Richard Cochran <richardcochran@gmail.com>\nCc: Shuah Khan <shuahkh@osg.samsung.com>\nLink: http://lkml.kernel.org/r/1464807207-16530-2-git-send-email-john.stultz@linaro.org\nSigned-off-by: Thomas Gleixner <tglx@linutronix.de>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/dfc2507b26af22b0bbc85251b8545b36d8bc5d72"},{"sha":"e2dfb4b880146bfd4b6aa8e138c0205407cebbaf","author":{"name":"Russell King","email":"8640768d851c67eb4c0e8bfcf2aabcc8010b9372@armlinux.org.uk"},"message":"ARM: fix PTRACE_SETVFPREGS on SMP systems\n\nPTRACE_SETVFPREGS fails to properly mark the VFP register set to be\nreloaded, because it undoes one of the effects of vfp_flush_hwstate().\n\nSpecifically vfp_flush_hwstate() sets thread->vfpstate.hard.cpu to\nan invalid CPU number, but vfp_set() overwrites this with the original\nCPU number, thereby rendering the hardware state as apparently \"valid\",\neven though the software state is more recent.\n\nFix this by reverting the previous change.\n\nCc: <stable@vger.kernel.org>\nFixes: 8130b9d7b9d8 (\"ARM: 7308/1: vfp: flush thread hwstate before copying ptrace registers\")\nAcked-by: Will Deacon <will.deacon@arm.com>\nTested-by: Simon Marchi <simon.marchi@ericsson.com>\nSigned-off-by: Russell King <rmk+kernel@armlinux.org.uk>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/e2dfb4b880146bfd4b6aa8e138c0205407cebbaf"},{"sha":"dd5f1b049dc139876801db3cdd0f20d21fd428cc","author":{"name":"Marc Zyngier","email":"3404add73d8af5dc5183acdd46985971473febc7@arm.com"},"message":"irqchip/gic-v3: Fix ICC_SGI1R_EL1.INTID decoding mask\n\nThe INTID mask is wrong, and is made a signed value, which has\nnteresting effects in the KVM emulation. Let's sanitize it.\n\nCc: stable@vger.kernel.org\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/dd5f1b049dc139876801db3cdd0f20d21fd428cc"},{"sha":"fab0cdc30d81694d2d5524b24e42c43414971719","author":{"name":"Andrew Jones","email":"6ce2cb60417f1f39ff6de3c1d0daaec5876c1c5a@redhat.com"},"message":"irqchip/gic-v3: Fix copy+paste mistakes in defines\n\nICC_SGI1R_AFFINITY_{2,3}_MASK are unused, which is good\nbecause they were defined with the wrong shifts.\n\nSigned-off-by: Andrew Jones <drjones@redhat.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/fab0cdc30d81694d2d5524b24e42c43414971719"},{"sha":"cf1d9d11e25053a264c0001aa86be7680bb1ecc1","author":{"name":"Andrew Jones","email":"6ce2cb60417f1f39ff6de3c1d0daaec5876c1c5a@redhat.com"},"message":"irqchip/gic-v3: Fix quiescence check in gic_enable_redist\n\nMake sure the two sides of the bitwise operation are bool.\n\nSigned-off-by: Andrew Jones <drjones@redhat.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/cf1d9d11e25053a264c0001aa86be7680bb1ecc1"},{"sha":"fbf8f40e1658cb2f17452dbd3c708e329c5d27e0","author":{"name":"Ganapatrao Kulkarni","email":"4c7e3086bb737bd045c665f311d207d879edf0c4@caviumnetworks.com"},"message":"irqchip/gicv3-its: numa: Enable workaround for Cavium thunderx erratum 23144\n\nThe erratum fixes the hang of ITS SYNC command by avoiding inter node\nio and collections/cpu mapping on thunderx dual-socket platform.\n\nThis fix is only applicable for Cavium's ThunderX dual-socket platform.\n\nReviewed-by: Robert Richter <rrichter@cavium.com>\nSigned-off-by: Ganapatrao Kulkarni <gkulkarni@caviumnetworks.com>\nSigned-off-by: Robert Richter <rrichter@cavium.com>\nSigned-off-by: Marc Zyngier <marc.zyngier@arm.com>","distinct":false,"url":"https://api.github.com/repos/olivieer/kernel_msm-3.10/commits/fbf8f40e1658cb2f17452dbd3c708e329c5d27e0"}]}
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