{"repository":{"description":"A VHDL UART for communicating over a serial link with an FPGA","watchers":3,"stargazers":3,"forks":2,"fork":false,"size":180,"owner":"pabennett","private":false,"open_issues":1,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"VHDL","created_at":"2013-01-31T10:33:37-08:00","pushed_at":"2013-07-07T11:22:13-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Peter Bennett","blog":"www.bytebash.com","location":"UK","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/pabennett/uart/pull/2"}