{"repository":{"description":"Power-PC  & FPGA dual-core system","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":372,"owner":"cbl709","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-06-04T22:54:52-07:00","pushed_at":"2013-08-28T23:54:14-07:00","master_branch":"master"},"actor_attributes":{"type":"User","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/cbl709/Dual-Core-System/compare/9b489aca6a...6b94920cff"}