{"repository":{"description":"HDL Lab Repo","homepage":"","watchers":0,"stargazers":0,"forks":1,"fork":false,"size":45162,"owner":"juehv","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-08-07T01:47:54-07:00","pushed_at":"2013-08-17T07:24:09-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Jens Heuschkel","company":"JUehV Tech","blog":"www.juehv-tech.de","location":"Germany","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/juehv/hdl-lab/compare/c93eeea8ab...ba1423dcb5"}