{"repository":{"description":"","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":1780,"owner":"juehv","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-11-14T06:34:34-08:00","pushed_at":"2013-11-14T06:43:18-08:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Jens Heuschkel","company":"JUehV Tech","blog":"www.juehv-tech.de","location":"Germany","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/juehv/RS2/compare/c4a3c137f2...ae8b5eede0"}