{"repository":{"description":"Altera Quartus Project for OpenBTS USRP1 Cyclone FPGA bitstream ","homepage":"","watchers":3,"stargazers":3,"forks":1,"fork":false,"size":6344,"owner":"closehaulcom","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2011-07-29T09:24:46-07:00","pushed_at":"2012-03-14T18:13:52-07:00","master_branch":"master"},"actor_attributes":{"type":"User","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/closehaulcom/usrp1_openbts"}