{"repository":{"description":"This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) algorithm and implemented through Field Programmable Gate Array (FPGA). This is a very optimized code for handling IP packets and encrypt/decrypt the data part using a  128-bit block cipher. It uses a pipeline and sub pipeline architecture.","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":168,"owner":"kalpataru","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"created_at":"2013-04-30T23:39:37-07:00","pushed_at":"2013-05-02T11:39:02-07:00","master_branch":"master"},"actor_attributes":{"type":"User","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/kalpataru/IP_Stream_Encryption_using_AES_and_FPGA/compare/28da33fc15...518b99e495"}