{"repository":{"description":"FPGA Design Suite featuring a component library, schematic entry, and C to Verilog design flow.","homepage":"www.pyandchips.org","watchers":2,"stargazers":2,"forks":1,"fork":false,"size":4203,"owner":"dawsonjon","private":false,"open_issues":8,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Python","created_at":"2011-11-26T03:11:04-08:00","pushed_at":"2013-12-16T12:32:24-08:00","master_branch":"master"},"actor_attributes":{"type":"User","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/dawsonjon/Chips-2.0/issues/25"}