{"repository":{"description":"A VHDL generator made with Python","watchers":0,"stargazers":0,"forks":1,"fork":false,"size":84,"owner":"andrecp","private":false,"open_issues":1,"has_issues":true,"has_downloads":true,"has_wiki":true,"created_at":"2013-07-28T10:33:42-07:00","pushed_at":"2013-07-28T15:37:58-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Fabio Utzig","company":"","blog":"http://utzig.net","location":"Brazil","email":"223bb78da41f44447ff0ad216d5a49d6b0f1c366@utzig.net"},"url":"https://github.com/andrecp/vhdl_gen/pull/1"}