{"repository":{"description":"Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools","watchers":3,"stargazers":3,"forks":0,"fork":false,"size":1540,"owner":"jamieiles","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-07-03T10:14:38-07:00","pushed_at":"2013-09-27T12:11:18-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Anthony Green","blog":"http://www.moxielogic.org/blog","location":"Toronto, Ontario, Canada","email":"bc74f4f071a5a33f00ab88a6d6385b5e6638b86c@moxielogic.com"},"url":"https://github.com/jamieiles/oldland-cpu"}