{"repository":{"description":"Improved Quartus BDF to Verilog File Conversion","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":0,"owner":"IdleLogic","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"created_at":"2013-08-09T09:38:15-07:00","pushed_at":"2013-08-09T09:38:15-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Chris Zeh","blog":"www.idle-logic.com","location":"San Jose, CA","email":"1001b22c8e4adeb77ef10481ad06ff9c35006cb3@idle-logic.com"},"url":"https://github.com/IdleLogic/b2vFixer"}