{"repository":{"description":"Automatically generate verilog module ports,instance and instance connections ,for sublime text 2&3","homepage":"","watchers":2,"stargazers":2,"forks":1,"fork":false,"size":166,"owner":"Tian-Changsong","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Python","created_at":"2013-04-04T01:23:48-07:00","pushed_at":"2013-08-06T01:12:13-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"田长松","company":"Tianjin university","blog":"http://www.cnblogs.com/tshell/","location":"中国，天津","email":"506fe1edb2edd21acac5e64ba95cbcf272d31b8d@126.com"},"url":"https://github.com/Tian-Changsong/Verilog-Automatic/issues/2"}