{"repository":{"description":"A collection of big designs to run post-synthesis simulations with yosys","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":504,"owner":"cliffordwolf","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-11-16T14:36:40-08:00","pushed_at":"2013-11-19T07:47:17-08:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Clifford Wolf","blog":"http://www.clifford.at/","location":"Vienna","email":"b28e7ff75903c06de987a1eb75ea100a79c89e3a@clifford.at"},"url":"https://github.com/cliffordwolf/yosys-bigsim/compare/1f1d651a2f...23efc55910"}