{"repository":{"description":"Xilinx Spartan6 LX45 device:XC6SLX45 package:CSG324 example projects written in VHDL using Xilinx ISE and Digilent Adept runtime+utils","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":744,"owner":"cf16","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"VHDL","created_at":"2013-10-20T11:19:32-07:00","pushed_at":"2013-10-21T13:11:42-07:00","master_branch":"master"},"actor_attributes":{"type":"User","blog":"www.cf16.eu","location":"Warsaw, Poland","email":"97607be36098a11ebbd418e8cb692e80c46220f1@cf16.eu"},"url":"https://github.com/cf16/fpga/compare/ef79382d26...7610dc57a9"}