{"repository":{"open_issues":0,"owner":"jwarchal","has_downloads":true,"watchers":0,"created_at":"2013-02-01T08:41:59-08:00","has_wiki":true,"description":"VHDL Single Cycle Processor Design for ECE 4440 at UVa.  Team Hichi!","stargazers":0,"fork":false,"size":112,"pushed_at":"2013-02-01T10:03:05-08:00","forks":0,"private":false,"has_issues":true},"actor_attributes":{"type":"User","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/jwarchal/ADD_SingleCycle/compare/37a7a24255...f9c4131dfe"}