{"repository":{"description":"My SimpleCPU Verilog project, as part of CS240 Computer Architecture course in Özyeğin University.","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":112,"owner":"aemreunal","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-06-18T04:13:05-07:00","pushed_at":"2013-06-18T04:19:23-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"A. Emre Ünal","blog":"www.flickr.com/aemreunal","location":"","email":"549a78dddd2604a95a46248cd49de93650cab42f@gmail.com"},"url":"https://github.com/aemreunal/SimpleCPU/compare/master"}