{"repository":{"description":"SDRAM controller with multiple wishbone slave ports","watchers":0,"stargazers":0,"forks":2,"fork":false,"size":120,"owner":"skristiansson","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-08-27T11:47:34-07:00","pushed_at":"2013-09-05T22:33:07-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Olof Kindgren","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/olofk/wb_sdram_ctrl"}