{"repository":{"description":"An example of random verification for verilog RTL module with QuickCheck library of Haskell.","watchers":0,"stargazers":0,"forks":1,"fork":false,"size":276,"owner":"h-hirai","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-04-30T22:03:40-07:00","pushed_at":"2013-05-01T20:53:32-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"keita goto","blog":"http://twitter.com/_k_goto","location":"tokyo, japan","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/k-goto/AnExampleForQuickCheckVerilog"}