{"repository":{"description":"A Verilog HDL model of the MOS 6502 CPU","homepage":"http://ladybug.xs4all.nl/arlet/fpga/6502/","watchers":12,"stargazers":12,"forks":4,"fork":false,"size":124,"owner":"Arlet","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2011-05-02T10:01:23-07:00","pushed_at":"2012-10-06T07:22:25-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Charles Eric LaForest","blog":"http://www.eecg.utoronto.ca/~laforest/","email":"7520047b3fc93afabfa999422c5e7d496eb2b097@eecg.utoronto.ca"},"url":"https://github.com/Arlet/verilog-6502"}