{"repository":{"description":"A simple 4-bit CPU created in Verilog for the Hardware Lab course at IIT Patna.","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":44,"owner":"g-karthik","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"created_at":"2013-08-10T05:23:33-07:00","pushed_at":"2013-08-10T05:30:07-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Karthik","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/g-karthik/SimpleCPU/compare/4985d846ea...93d3048942"}