{"repository":{"description":"Final Year Project 2013 - SDRAM Memory Refresh Control","homepage":"","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":1624,"owner":"chenyushe","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-06-18T05:51:49-07:00","pushed_at":"2013-07-01T03:05:24-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"chenyushe","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/chenyushe/FYP2013/compare/ed16e1191c...ef35f19b5b"}