{"repository":{"has_wiki":true,"stargazers":0,"owner":"Jarob22","has_issues":true,"created_at":"2013-01-29T17:17:23-08:00","description":"A repo for what will be a fully functioning CPU written in VHDL","language":"VHDL","fork":false,"size":3044,"has_downloads":true,"open_issues":0,"private":false,"pushed_at":"2013-02-06T08:23:20-08:00","watchers":0,"forks":0},"actor_attributes":{"type":"User","company":"Student","location":"England","email":"474ba67bdb289c6263b36dfd8a7bed6c85b04943@jamesreed.name","name":"James"},"url":"https://github.com/Jarob22/dsa_cpu/compare/4813d49d51...5937b22012"}