{"repository":{"description":"Generic VHDL Edge Detector","watchers":1,"stargazers":1,"forks":0,"fork":false,"size":232,"owner":"wltr","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"VHDL","created_at":"2013-07-03T08:55:20-07:00","pushed_at":"2013-07-14T23:54:26-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Johannes Walter","blog":"http://wltr.at/","email":"8398eb9892c5ab2ff439ca0b5e4b0706dd9ebef9@wltr.at"},"url":"https://github.com/wltr/vhdl-edge-detector/compare/4b00b965c9...6ac84f8fca"}