{"repository":{"description":"SDRAM controller with multiple wishbone slave ports","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":128,"owner":"skristiansson","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-08-27T11:47:34-07:00","pushed_at":"2013-09-03T22:22:49-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Stefan Kristiansson","location":"Espoo, Finland","email":"76f148d6211905cb33a2dc66f1e38f54cf3e5294@saunalahti.fi"},"url":"https://github.com/skristiansson/wb_sdram_ctrl/compare/5c105e5604...398049e38d"}