{"repository":{"description":"vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":62,"owner":"pliu6","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Verilog","created_at":"2013-08-18T12:03:48-07:00","pushed_at":"2013-08-18T12:05:14-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Peng Liu","location":"Madison, WI","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/pliu6/vhd2vl/compare/master"}