{"repository":{"description":"A Universal Asynchronous Receiver Transmitter designed in VHDL. It connects to a Hyperterminal through an FPGA board.  ","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":740,"owner":"anandsoni11","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"VHDL","created_at":"2013-06-05T07:29:06-07:00","pushed_at":"2013-06-05T07:32:11-07:00","master_branch":"master"},"actor_attributes":{"type":"User","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/anandsoni11/UART/compare/master"}