{"repository":{"description":"Automatically generate verilog module ports,instance and instance connections","homepage":"","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":140,"owner":"Tian-Changsong","private":false,"open_issues":1,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"Python","created_at":"2013-04-04T01:23:48-07:00","pushed_at":"2013-07-29T21:45:19-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"João Carlos","company":"Universidade Estadual de Feira de Santana","blog":"","location":"Feira de Santana","email":"1f6360cccde12bbe1d91eed46a5777375dd79b9b@ecomp.uefs.br"},"url":"https://github.com/Tian-Changsong/Verilog-Automatic/issues/2"}