{"repository":{"description":"A VHDL UART for communicating over a serial link with an FPGA","watchers":2,"stargazers":2,"forks":1,"fork":false,"size":152,"owner":"pabennett","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"VHDL","created_at":"2013-01-31T10:33:37-08:00","pushed_at":"2013-02-16T07:00:32-08:00","master_branch":"master"},"actor_attributes":{"type":"User","blog":"https://sethdepot.org","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/sd2k9/uart"}