{"repository":{"description":"RISC CPU basic inner structures from my College Final year's project.","homepage":"","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":152,"owner":"asafw","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"language":"VHDL","created_at":"2013-09-16T14:41:03-07:00","pushed_at":"2013-09-16T15:00:44-07:00","master_branch":"master"},"actor_attributes":{"type":"User","email":"da39a3ee5e6b4b0d3255bfef95601890afd80709"},"url":"https://github.com/asafw/RISC_CPU_VHDL/compare/a2e662d78d...ed4c5f530f"}