{"repository":{"description":"Extended Verilog, adds features to verilog and converts xverilog to synthesisable verilog","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":0,"owner":"wnew","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"created_at":"2013-08-06T07:07:55-07:00","pushed_at":"2013-08-06T07:07:55-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Wesley New","email":"a68283aa4922ba6bf66ede4560fa13dd64ea6ddb@ska.ac.za"},"url":"https://github.com/wnew/xverilog"}