{"repository":{"description":"Set of Beginner to Intermediate Verilog Codes","watchers":0,"stargazers":0,"forks":0,"fork":false,"size":0,"owner":"smhegde","private":false,"open_issues":0,"has_issues":true,"has_downloads":true,"has_wiki":true,"created_at":"2013-03-12T02:20:35-07:00","pushed_at":"2013-03-12T02:20:36-07:00","master_branch":"master"},"actor_attributes":{"type":"User","name":"Subramanya","email":"f660c6dddb71114fc3166fd1d85b1707133d3590@gmail.com"},"url":"https://github.com/smhegde/Verilog"}