Semiconductor chips typically are connected to external circuitry through contacts on a surface of the chip. The contacts on the chip typically are disposed in the regular patterns such as a grid substantially covering the front surface of the chip, commonly referred to as an "area array" or in elongated rows extending along each edge of the chip front surface. Each contact on the chip must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes for making these interconnections use prefabricated arrays of leads or discrete wires. For example, in a wirebonding process, the chip is physically mounted on the substrate. A fine wire is fed through a bonding tool. The tool is brought into engagement with the contact on the chip so as to bond the wire to the contact. The tool is then moved to a connection point of the circuit on the substrate, so that a small piece of wire is dispensed and formed into a lead, and connected to the substrate. This process is repeated for every contact on the chip.
In the so-called tape automated bonding or "TAB" process, a dielectric supporting tape, such as a thin foil of polyimide is provided with a hole slightly larger than the chip. An array of metallic leads is provided on one surface of the dielectric film. These leads extend inwardly from around the hole towards the edges of the hole. Each lead has an innermost end projecting inwardly, beyond the edge of the hole. The innermost ends of the leads are arranged side by side at spacing corresponding to the spacings of the contacts on the chip. The dielectric film is juxtaposed with the chip so that the hole is aligned with the chip and so that the innermost ends of the leads will extend over the front or contact bearing surface on the chip. The innermost ends of the leads are then bonded to the contacts of the chip, as by ultrasonic or thermocompression bonding. The outer ends of the leads are connected to external circuitry.
In a so-called "beam lead" process, the chip is provided with individual leads extending from contacts on the front surface of the chip outwardly beyond the edges of the chip. The chip is positioned on a substrate with the outermost ends of the individual leads protruding over contacts on the substrate. The leads are then engaged with the contacts and bonded thereto so as to connect the contacts on the chip with contacts on the substrate.
The rapid evolution of a semiconductor art in recent years has created a continued demand for progressively greater numbers of contacts and leads in a given amount of space. An individual chip may require hundreds or even thousands of contacts, all within the area of the chip front surface. For example, a complex semiconductor chip in current practice may have a row of contacts spaced apart from one another at center-to-center distances of 0.5 mm or less and, in some cases, 0.15 mm or less. These distances are expected to decrease progressively with continued progress in the art of semiconductor fabrication.
With such closely-spaced contacts, the leads connected to the chip contacts, must be extremely fine structures, typically less than 0.1 mm wide. Such fine structures are susceptible to damage and deformation. With closely spaced contacts, even minor deviation of a lead from its normal position will result in misalignment of the leads and contacts. Thus, a given lead may be out of alignment with the proper contact on the chip or substrate, or else it may be erroneously aligned with an adjacent contact. Either condition will yield a defective chip assembly. Errors of this nature materially reduce the yield of good devices and introduce defects into the product stream. These problems are particularly acute with those chips having relatively fine contact spacings and small distances between adjacent contacts.
It has been proposed to form a prefabricated lead assembly having inwardly projecting leads with all of the inner ends of the leads connected to a common inner element. The common element typically is a metallic ring-like structure. In these structures, the inner end of each lead is connected to the common element via a frangible section. The common element thus restrains the inner ends of the leads against relative movement and hence inhibits bending or other deformation of the leads. After the leads have been bonded to the chip contact, the common element is broken away from the leads. A frangible section may be provided at the juncture between the innermost end of each lead and the inner element. Systems of this nature are illustrated, for example, in Thorpe, Jr. U.S. Pat. No. 4,756,080 and in Angelucci, Sr. et al, U.S. Pat. No. 4,380,042. Burns, U.S. Pat. Nos. 4,312,926 and 4,413,404 depict a generally similar arrangement in which the leads are multilayer metallic structures including a copper base with an overcoat of nickel. The frangible connection between the innermost end of each lead and the inner element consists solely of the nickel overcoat layer, thereby providing a very thin, weak section.
In these arrangements, the common element electrically interconnects all of the leads. These interconnections must be eliminated after the leads have been bonded to the chip. Thus, the common element must be pulled away from the chip after the leads have been bonded to the contacts of the chip. All of the frangible elements must be broken either simultaneously or in a particular pattern as the common element is pulled away from the innermost ends of the leads. The need to remove the common element constitutes a significant drawback, inasmuch as this must be done without disturbing the delicate bonds between the lead ends and the contacts on the chip. Perhaps for these reasons, systems utilizing a common element have not been widely adopted.
Thus, despite the substantial time and effort devoted heretofore to the problems associated with mounting and connecting of semiconductors, there have still been substantial, unmet needs for improvements in such processes and in the equipment and components used to practice the same.