1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit (IC) for supporting a test mode.
2. Related Art
In general, most semiconductor memory manufacturers are developing Phase change Random Access Memory (PRAM) device that make use of phase changing materials to store data as one of the next generation of memory devices. A PRAM device is a non-volatile memory device that makes use of materials for storing data, such as germanium (Ge), anitmony (Sb), and tellurium (Te) (hereinafter abbreviated as GST), wherein the resistance of the GST material changes as the amorphous/crystalline phases are changed in accordance with changes in temperature of the GST material.
Commonly, semiconductor integrated circuits using non-volatile memory devices, such as PRAM devices include a user's program region, i.e., a One Time Programmable (OTP) region. More specifically, a user is able to store information regarding the device including a serial number of a product, an identification number (ID) of the utilized device, the date of manufacture, and a security number, for example, in the OTP region. Just like a memory region that stores conventional data, the OTP region can include a predetermined memory cell array that is electrically erasable and programmable.
However, when the OTP region is only located in one side of a bank structure, the structure of the entire bank is not symmetric, thereby restricting arrangement of circuits on the semiconductor IC. In addition, a separate OTP decoder is required for providing cell access to the OTP region. Furthermore, if a cell within the OTP region is determined to be faulty, a redundant circuit and a control technique are required to replace the faulty cell with another normal cell in the OTP region.