Memory devices are commonly employed as internal storage areas in a computer or other type of electronic equipment. One specific type of memory used to store data in a computer is random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM), for example. A typical SRAM device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value that represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With complementary metal oxide semiconductor (CMOS) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch that stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor (6T) cell, a pair of access transistors or pass gates (when activated by a word line) selectively couples the inverters to a pair of complementary bit lines. Other SRAM cell designs may include a different number of transistors, e.g., 4T, 8T, etc.
Static power and dynamic power constitute the two main components of total power used by memory devices such as SRAM. Static power essentially consists of the power used when a transistor is not in the process of switching and may be determined by the formula: P=Istatic(Vdd). Where Vdd is the supply voltage and Istatic is the total current flowing through the memory device. Dynamic power essentially consists of transient power consumption and capacitive load power consumption. Transient power consumption represents the amount of power consumed when the memory device changes logic states, e.g., “0” bit to “1” bit or vice versa. Capacitive load power consumption represents the power used to charge the load capacitance. Dynamic power may be determined by the formula: P=C(Vdd)2f. Where C is the capacitance, Vdd is the supply voltage, and f is the frequency.
Due to rapid advancement in very large scale integration technology over the last couple decades, aggressive scaling of CMOS transistor dimensions is becoming a trend in order to achieve high package density chips and improved performance. Supply voltage and threshold voltage are also scaled in order to maintain the reliable operation of the transistors. Dynamic power in SRAM is becoming a big concern with scaling because with the scaling in supply voltage, metal width, and spacing, the power consumption of the SRAM is assumed to scale down by 50%. However, the power consumption of the SRAM is not scaling as much as assumed with the scaling of supply voltage, metal width, and spacing in very large scale integration technology.
In SRAM devices, the major part of dynamic power consumption comes from read power because read activity can be as high as about 90% on a memory device. Specifically, read global bit line switching or toggling power (i.e., transient power consumption) is one of the major contributors to the total read power. Reducing metal width, increasing metal spacing, and reducing supply voltage are some common practices that are followed for reducing the power consumption. However, reducing the metal width increases resistance, which diminishes performance, increasing metal spacing increases the metal pitch, which affects the area of the device, and the performance of the SRAM cell is significantly affected at low supply voltages. Accordingly, new methods to reduce power consumption of SRAM devices are needed over merely reducing metal width, increasing metal spacing, and reducing supply voltage.