The present invention relates to methods for providing uniform, planar integrated circuit (IC) wafer surfaces and removing tungsten stringers from such surfaces. More particularly, the present invention relates to photolithography and etching procedures for achieving these goals.
FIG. 1 shows a top view of a typical semiconductor wafer 10 having an active die region 12 and a peripheral region 14. Transistor devices, such as metal oxide semiconductor (MOS) transistor devices, are located in the ICs (die) that make up die region 12. Peripheral region 14 or the "exclusion zone," as it is known, is the part of the wafer surrounding die region 12. Peripheral region 14, tends to be relatively large, i.e. typically about 1 cm or more (in the radial direction) from the edge of wafer 10.
It has been found that by the end of the IC fabrication process, this peripheral region is typically elevated about 3-5 micrometer (.mu.m) above die region 12. The difference in the height of die region 12 and peripheral region 14 results from material build-up in peripheral region 14 during conventional wafer fabrication processes.
Most IC wafer fabrication processes can be divided into "front end" steps and "back end" steps. Front end steps generally include those steps necessary to form the actual transistor elements such as source/drain regions, gates, and isolation regions. Back end steps generally include those process steps necessary to create circuitry by wiring the various transistors formed by the front end processing. The material build up in the peripheral region of the wafer surface is primarily a result of the back end steps.
FIGS. 2A-2J show a cross-section of a semiconductor wafer surface that undergoes typical back end steps, which result in the material build up in the peripheral region. It should be noted that metal oxide semiconductor (MOS) transistor elements, for example, are formed near the semiconductor surface, but are not shown to simplify illustration.
According to a conventional wafer fabrication process, a gate layer, e.g., a layer of polysilicon, is blanket deposited on the semiconductor wafer surface including a die region and a peripheral region. Portions of the wafer surface are thereafter appropriately masked where, for example, gate electrodes and gate level jumpers for connecting the various transistor elements, are to be formed. FIG. 2A shows polysilicon structures 16 that are formed by anisotropically etching the polysilicon disposed above the surface of wafer 10. It is important to note that the polysilicon layer in die region 12 undergoes etching as desired, but a substantial amount of the polysilicon layer in peripheral region 14 remains unetched. Peripheral region 14 remains unetched primarily because patterning of the layer of photoresist that takes place in the die region to form die is not carried out in the peripheral region where die are not present.
After polysilicon structures 16 are formed, dielectric layer 18, as shown in FIG. 2B, is conformally deposited over the entire wafer surface of FIG. 2A in order to insulate polysilicon structures 16 from a subsequent metallization layer. Dielectric layer 18 is commonly referred to as an inter layer dielectric 1 (ILD1) in the wafer fabrication art. FIG. 2C shows that dielectric layer 18 is then planarized by a process such as chemi-mechanical polishing, which involves mounting a wafer upside down on a holder and rotating it on against a polishing pad mounted on a pallet, which is rotating in the other direction. A slurry containing a chemical capable of dissolving the wafer layer to be planarized and an abrasive that physically removes the layer to be planarized, is flowed between the wafer and the polishing pad.
It should be noted that during planarization, the narrow protuberances of dielectric above the etched metal lines are almost completely removed to form a planarized dielectric layer 19, while the material removal in the peripheral region is relatively insignificant. Dielectric layer 19 in the die region is, therefore planarized to a relatively low level, while dielectric layer portion 18 in the peripheral region remains elevated. This is because dielectric layer 18 in the peripheral region remains deposited on the unetched portions of gate layer 16.
Next, a via mask is formed on the upper surface of dielectric layer 19 by forming a layer of photoresist and using conventional photolithography techniques to pattern the layer of photoresist. The via mask will define vias or regions where interconnects between polysilicon structures 16 and a subsequent metallization layer are to be formed. FIG. 2D shows the formation of actual vias 20 in dielectric layer 19. Such vias are typically formed by a plasma assisted etch.
As shown in FIG. 2E, a conductive layer 22, e.g., tungsten or aluminum, is then deposited over the entire wafer surface, filling vias 20 of FIG. 2D. Next, conductive plugs 24, as shown in FIG. 2F, are formed by subjecting the entire wafer surface to chemi-mechanical polishing described above. During chemi-mechanical polishing, the die region of the wafer surface undergoes significant material removal and conductive layer 22 is removed in the open areas to form conductive plugs 24. In the peripheral region, however, the accumulated build, e.g., polysilicon structure 16 and ILD1, impairs the polishing process because the polishing pad rides up at the peripheral region and thereby exerts a lower polish pressure per square inch in the peripheral region than in the die region. As a result, a portion of conductive layer 22 does not undergo material removal during chemi-mechanical polishing in the peripheral region, where a significant portion of conductive layer 22 remains on the non-planarized dielectric layer 18. This residual conductive layer, which may include tungsten as mentioned above, in the peripheral region is well known in the art as a "tungsten stringer" and is discussed below.
FIG. 2G shows a first metallization layer (M1) 26, which is blanket deposited over the entire wafer surface typically by sputtering or chemical vapor deposition, as is well known in the IC fabrication art. In FIG. 2H, metallization layer 26 is patterned (in the die region only) as described below to form lines 28. As shown in this figure, near the peripheral region, one of lines 28 contacts tungsten stringer 22. For the sake of maintaining continuity, the effects of having lines 28 very close to or contacting tungsten stringer 22 will be discussed below in detail.
Lines 28 typically form a network of connections between the various transistor elements. The exact layout of the lines will be determined by the particular IC or ASIC design. The patterning is done first by depositing a mask such as a photoresist and then exposing only the mask in the die region to light to define the pattern of metal lines to be created in a subsequent etch step. Thereafter, according to FIG. 2H, the underlying first metallization layer in the die region is etched by a plasma process such as reactive ion etching (RIE) to form lines 28.
After etching, the photoresist is removed and another dielectric layer 32, also referred to as inter layer dielectric 2 (ILD2) or Inter Metal Dielectric (IMD), is conformally deposited over the entire wafer surface and then planarized in the die region to form a planarized dielectric layer 34 as shown in FIG. 21. Dielectric layer 32 is typically planarized by chemi-mechanical polishing. However, the accumulated build up, e.g., polysilicon structure 16, ILD1, and M1, in the peripheral region substantially impairs the polishing process because the polishing pad significantly rides up at the peripheral region. As a result, even after polishing, the wafer surface has a significant variation in the surface topography.
As shown in FIG. 2J, vias 36 are then formed in dielectric layer 34 as already described above in the discussion corresponding to FIG. 2D.
Unfortunately, near the peripheral region a via 36' may not extend all the way to contact line 26, as shown in FIG. 2J. The formation of such vias and their effects are described below in significant detail.
These vias are then filled with a conductive layer, which is etched in the die region according to the discussion corresponding to FIG. 2F, to form conductive plugs. The unetched conductive layer in the peripheral region is disposed above non-planarized dielectric layer 32, further contributing to the accumulated build up.
One skilled in the art may appreciate that in this manner more dielectric and metallization layers may be fabricated over the wafer surface. Furthermore, as layer after layer of metallization and dielectric material are fabricated, the peripheral region of the wafer surface experiences a significant build up or accumulation of such layers. This results in a "step profile," i.e. the various layers described above form a stacked structure in the peripheral region.
Unfortunately, the conventional method of wafer fabrication, as described above, has several drawbacks. These drawbacks are well known in the art as being caused by the material build up at the peripheral region of the wafer surface and referred to as shadow effects. Referring back to FIG. 1, which shows an edge die 100 abutting peripheral region 14. At least one side of the edge die is, therefore, adjacent to the significant material build up of the peripheral region. FIG. 3 shows edge die 100 magnified to emphasize details of interest. As shown in this figure, edge die 100 has a plurality of bond pads 102 around the perimeter of the die. Thus, some bond pads 102 will be surrounded by the build up of the peripheral region.
As an example of a first drawback, before the etching step of FIG. 2J is performed to form vias, the material build up in the peripheral region causes poor planarization of ILD2. The variation of the surface topography, especially near the peripheral region, remains pronounced even after the wafer surface undergoes chemi-mechanical polishing. As a result, subsequent photolithography exposures are limited by uneven depth of field (DOF) during imaging when forming masks for vias near the peripheral region and thereby the etching step to form vias suffers significantly.
As another example, the material build up in the peripheral region may not allow the etching to continue far enough near the peripheral region into ILD2 so that the vias fail to extend far enough to contact the underlying metallization layer, as shown in FIG. 2J. In order to establish contact with the underlying metallization, the vias in the die region are typically etched about 4000 .ANG. into the dielectric layer. Due to the non-uniform surface, however, the vias near the peripheral region may require etching distances of up to 7000 .ANG. to establish contact with the underlying metallization. Thus, when ILD2 undergoes etching to form vias, it has sometimes been observed that connections to bond pads and other structures located near the peripheral region may not completely extend to the underlying metallization, rendering the entire die inoperable. Overetching might be able to form contacts to the underlying metallization, but has side effects like loss of process control, critical dimension variation, lateral etching etc.
As a further example, the formation of conductive lines 28 near the peripheral region, as shown in FIG. 2H, may undesirably come in contact with the tungsten stringer to create a short circuit, rendering the edge die inoperable. These examples illustrate a few problems resulting from elevated peripheral regions produced in a conventional wafer fabrication process. Each of these problems lowers the yield of the die fabrication process.
What is needed is a method for effectively fabricating dies on an IC wafer surface and boosting the die yield, especially near the peripheral region.