1. Technical Field
Various embodiments of the present invention relate to a three-dimensional (3D) semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to a 3D semiconductor integrated circuit capable of improving gate pick-up failures, and a method of manufacturing the same.
2. Related Art
With the rapid development of mobile and digital information communication and the consumer-electronic industry, studies on existing electronic charge controlled-devices may encounter limitations. To overcome the limitations, new functional memory devices having novel designs need to be developed. Particularly, next-generation memory devices with large capacities, ultra-high speed and ultra-low power need to be developed to satisfy demands of large capacity memories used in main information devices.
Resistive memory devices using a resistance material as a memory medium have been suggested as the next-generation memory devices, and typical examples of resistive memory devices are phase-change random access memories (PCRAMs), resistance RAMS (ReRAMs), or magnetic RAMS (MRAMs).
A resistive memory device may be typically formed of a switching device and a resistance device and may store data “0” or “1,” according to a state of the resistance device.
A final target of the resistive memory devices is to improve integration density and to integrate as many memory cells as possible in a limited small area. In recent years, methods of forming the resistive memory devices into 3D structures have been also suggested, and there is a growing need for a method of stably stacking a plurality of memory cells having narrower line width.
A typical method of manufacturing a resistive memory device having a 3D structure includes a method of forming a switching device using a vertical pillar as a vertical channel layer.
The 3D channel structure having a vertical pillar, has a vertical surround gate. The vertical surround gate structure may be formed to surround a lower region of the pillar. The vertical surround gates may form a gate pick-up in a predetermined region. The gate pick-up line may be electrically contacted to the gate using a general contact process. Since the gate is formed to surround a circumference of a lower portion of the pillar, an over-etching process is used to form a contact hole (hereinafter, referred to as a gate pick-up hole) for forming the gate pick-up line.
However, when using the over-etching process, the contact hole may penetrate a substrate region (for example, source region) located below the pillar, and thus a short circuit between the gate pick-up line and the substrate portion (for example, source region) of the pillar, may be caused.
As described above, as the gate is formed to surround the circumference of the lower portion of the pillar, the contact hole for forming the gate pick-up line also has a depth approaching a height of the pillar. Therefore, an aspect ratio of the contact hole in which the gate pick-up line is formed is increased, and thus a void may occur in the gate pick-up line.