1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a C-MOS (complementary metal-oxide semiconductor) type structure.
2. Description of the Prior Art
FIG. 5 illustrates a conventional semiconductor integrated circuit device 100 having a number of I/O (input/output) cells 90a, 90b, 90c, . . . , 90n formed therein. Each of such I/O cells typically has an output circuit in which a P-MOS transistor and an N-MOS transistor are connected in a C-MOS structure.
In this type of semiconductor integrated circuit device, in particular where very small transistors are formed as in an LSI chip, an increase in driving capacity is achieved by connecting a plurality of such CMOS structures in parallel as shown in FIG. 9. In FIG. 9, P1, P2, . . . , Pn represent P-MOS transistors; N1, N2, . . . , Nn represent N-MOS transistors; V.sub.DD represents a power source line; V.sub.SS represents a ground line; numeral 91 represents an output terminal.
Conventionally, two types of layout have been known for forming such an output circuit on a semiconductor substrate: the layout shown in FIG. 3 (a first conventional example) and the layout shown in FIG. 4 (a second conventional example). In FIG. 3, which shows the first conventional example, numeral 95 represents a wiring pattern, formed in a first wiring layer, that is connected to the source S1 of the P-MOS transistors by way of a contact hole 74 and connected to the source of the N-MOS transistors by way of a contact hole 84.
Numeral 96 represents another wiring pattern, also formed in the first wiring layer, that is similarly connected to the drain D1 of the P-MOS transistors by way of contact holes 75 and 76 and connected to the drain D1 of the N-MOS transistors by way of contact holes 85 and 86. Numeral 97 represents still another wiring pattern, also formed in the first wiring layer, that is connected to the source S2 of the P-MOS transistors by way of a contact hole 77 and connected to the source S2 of the N-MOS transistors by way of a contact hole 87.
Numeral 72 represents the gate electrode of the first P-MOS transistor, and numeral 73 represents the gate electrode of the second P-MOS transistor. On the other hand, numerals 82 and 83 represent the gate electrodes of the first and second N-MOS transistors, respectively. The power source line V.sub.DD and the ground line V.sub.SS are both formed as a wiring pattern in a second wiring layer.
In FIG. 4, which shows the second conventional example, the orientation of the transistors is different by 90 degrees as compared with the first conventional example. Numeral 101 represents a wiring pattern, formed in a third wiring layer, that serves to couple the P-MOS transistors with the N-MOS transistors. The power source line V.sub.DD and the ground line V.sub.SS are both formed as a wiring pattern in a second wiring layer. Numerals 102 to 106 represent wiring patterns formed in a first wiring layer.
When the number of transistors is increased to increase the driving capacity, the dimension WX shown in FIG. 3 that corresponds to the width of a single transistor needs to be multiplied by an integer. Whereas FIG. 3 shows a case where two transistors are formed on each of the P-MOS and N-MOS sides, FIG. 6A shows a case where six transistors are formed, a nd FIG. 6B shows a case where one more transistor is added thereto. Note that, for simplicity's sake, only the transistors on the P-MOS side are shown in FIGS. 6A and 6B. Here, the channel length of the transistors extends in the direction "X", and their channel width extends in the direction "Y".
In FIG. 6A, G1 to G6 represent the gate electrodes of the P-MOS transistors; that is, there are six P-MOS transistors. Here, addition of one more transistor is achieved, as shown in FIG. 6B, by increasing the number of transistors in the lateral direction. G7 represents the gate electrode of the added transistor.
However, as shown in FIG. 5, the size and shape of the I/O cells 90a to 90n are predetermined for each type of semiconductor integrated circuit device 100, and therefore, in most cases, it is simply impossible to increase the dimension XA any further. In such a case, in the first conventional example (FIG. 3), it is inevitable to increase the transistors in the direction "Y", as shown in FIG. 7. This, however, creates wasted space.
On the other hand, in the second conventional example (FIG. 4), where the channel length extends in the direction "Y" and the channel width extends in the direction "X", it is possible to increase the transistors efficiently in the direction "Y", as shown in FIG. 8. However, this second conventional example inconveniently requires a wiring pattern 101 (see FIG. 4) in a third wiring layer to connect the P-MOS side to the N-MOS side.