1. Field of the Invention
The present invention relates to a delta sigma (modulation) digital-to-analog converter (DAC) for digital audio equipment having a low distortion factor and a high S/N (signal to noise) ratio, and more particularly to a delta sigma digital-to-analog converter having a quantizer connected to a local digital-to-analog converter and having three or more quantizing levels.
2. Description of the Related Art
The delta sigma (modulation) DAC is widely used in audio equipment. The performance of a digital-to-analog converter in audio equipment is principally represented by factors such as a distortion factor (a ratio of a harmonic component to a signal) and a signal to noise (SIN) ratio. The performance of digital-to-analog converters in related art largely depends on absolute and relative variations in characteristics of components such as resistors and capacitors rather than circuit types, which variations are difficult to reduce in newer more precise components. Compared with this, in the delta sigma converter for which quantizing levels ranging only from two (1 bit) to several are required, the variations among components do not become a problem as in the related art converter. In recent years, however, higher performance has been required for digital-to-analog converters used in audio equipment so as to comply with the new 24 bit format of Digital Video Disc (DVD), as opposed to prior 16 bit format of Compact Disc (CD).
In order to improve the distortion factor and the S/N ratio, it is theoretically possible to increase any of the following: (1) the order of the delta sigma modulator; (2) the sampling frequency; or (3) the number of quantized levels (i.e., the number of bits) (See, e.g., xe2x80x9cAn oversampling A-D/D-A conversion technique (2)xe2x80x9d, Nikkei Electronics Aug. 8, 1988, No. 453, pp. 211-221).
An excessive increase in the order of the delta sigma modulator, however, is unsuitable for maintaining the stability of the feedback system called the xe2x80x9cnoise shaper.xe2x80x9d A noise shaper arithmetic unit is a one which converts a multi-bit digital signal, input by oversampling, to a digital signal with lower bits than those of the multi-bit digital signal by noise shaper operation and outputs it from a quantizer. Referring to FIG. 1, a third-order noise shaper arithmetic unit is shown which comprises multipliers Y1 and Y2, delay circuits Y3, Y4 and Y5, and adders Y6 and Y7. The delay circuits Y3, Y4 and Y5, which each provide a delay by one sampling period, are connected in series in numerical order. At adder Y6, an output from the delay circuit Y5 and outputs from the multipliers Y1 and Y2 are added to the input multi-bit digital signal (e.g., a 22 bit digital signal). At the multipliers Y1 and Y2, outputs from the delay circuits Y3 and Y4 are multiplied by coefficients 3 and xe2x88x923, respectively. The result of the addition output from adder Y6 is input to quantizer 1. The output of quantizer 1 is branched and subtracted from the input thereto at adder Y7 to be an input to delay circuit Y3. In FIG. 1, an arithmetic unit is shown in which a 22 bit digital signal is input for conversion to a 4 bit digital signal with 11 levels.
With respect to increasing the sampling frequency, i.e., increasing the operating frequency of the noise shaper arithmetic unit, this requires that the frequency of the system clock in the associated audio equipment be increased. This results in an increase in the cost of the audio equipment and in its power consumption, and also may cause interference noise in the analog audio system. As a result, the benefits of an increase in sampling frequency is limited to a certain extent.
In view of the foregoing, the best way to provide a delta sigma digital-to-analog converter with a reduced distortion factor and an improved S/N ratio is to adequately set the order of the delta sigma modulator and the sampling frequency therefor to increase the number of quantized levels. In order to adequately set the order of the delta sigma modulator and the sampling frequency therefor for increasing the number of quantized levels, a local digital-to-analog converter may be added which carries out a digital-to-analog conversion of the output of the built-in quantizer.
The resolution of the local digital-to-analog converter in the delta sigma modulation system is a minimum of 2 levels and at most several tens levels. Conventionally, Pulse Width Modulation (PWM) digital-to-analog converters or Dynamic Element Matching (DEM) digital-to-analog converters have been used in systems having three or more levels.
The PWM converter offers the advantage of higher precision because a plurality of levels are presented in a sampling period by using a clock frequency several times the sampling frequency, which clock frequency is provided by a highly precise quartz oscillator which determines the precision of conversion. However, the need to use an expensive high precision clock in PWM operation is a disadvantage of the PWM converter.
As for the DEM converter, a digital-to-analog converter is used with a plurality of converting elements for carrying out respective conversions at the same time. In this case, the DEM converter provides a delta sigma modulation in which the sampling frequency is set comparably high.
The DEM converter is provided with a plurality of analog elements such as resistors and capacitors, so that, when the elements are provided are included in an integrated circuit, the precision of the DEM converter depends on relative variations among elements which occur in the semiconductor production process for the integrated circuit. In order to reduce the influence of these variations on the precision of the converter, the DEM converter is operated so that all of the elements are configured so that they are equally used within a certain period of time according to a specified procedure. This method allows realization of better conversion precision than would result when simply relying upon the precision of the elements caused by the relative variations in the semiconductor production process.
A specific example of a prior art delta sigma digital-to-analog converter is shown in FIG. 2. Hereinafter, the multi-level digital-to-analog converter is referred as the multi-level DAC. In FIG. 2, the highest level of the multi-level DAC is shown as level 11 for ease of the explanation. In addition, twelve 1 bit local DACs are provided (LDAC1 to LDAC12). For ease of explanation, hereinafter the local DACs LDAC1 to IDAC12 are referred to as simply IDAC1 to LDAC12. In operation, there will be no case in which all of the IDAC1 to LDAC12 are turned on, that is, unit amounts are given to all of them. The digital-to-analog converter shown in FIG. 2 comprises a thermometer code converter 2 which outputs a thermometer code corresponding to the number of output levels from quantizer 1 (which is shown in detail in FIG. 1), a barrel shifter X3 which shifts in rotation a bit arrangement of the thermometer code very sampling period, IDAC1 to LDAC12 which are equally weighted to each other (i.e., provided with resistors with resistance values equal to each other), and an analog adder X4. The thermometer code converter 2 produces a thermometer code with the number of bits corresponding to the number of the output levels from quantizer 1. Along with this, barrel shifter X3 shifts in rotation the bit arrangement of the thermometer code to selectively supply currents (unit amounts) to the LDAC1 to LDAC12. The unit amount supplied to each of the local DAC""s is added to others to generate an analog output corresponding to the output levels of quantizer 1.
However, a conventional DEM converter shifts the thermometer code every sampling frequency period to supply in order the unit amount equally to the N local DACs and therefore has the following problem. The mode of rotation of the unit amount in the local DACs changes depending on the output data of quantizer 1 converted in a form of the thermometer code to cause distortion depending on the input data, as a result of which the converter is unsuitable for a DEM converter having multi-levels such as the eleven levels shown in FIG. 2. This is shown in the chart of FIG. 3, which presents the states at every period Ts for the sampling frequency fs about the unit amounts supplied to the LDAC1 to LDAC12, an integral value of errors in the local DACs, an integral value of the unit amounts in the LDAC1 to LDAC12, an averaged value of errors in the local DACs about the period, a cumulative average of errors in the local DACs, and an output level of the analog adder X4. As shown in FIG. 3, the thermometer code of 1 level is input to only one local DAC in one sampling period Ts. Therefore, as is apparent from FIG. 3, for a quantized output X lasting with level 1, it takes several cycles of Ts until all of the LDAC1 to LDAC12 are used. While, for a quantized output X with the higher number of levels almost all of the local DACs are used in 1 cycle of Ts. That is, the DEM converter has the disadvantage in that averaging of variations in local DACs tends to depend on signal values. In this regard, a simulation is carried out for the case where LDAC1 to LDAC12 have errors shown in the right upper column in FIG. 3. The result of the simulation shows that influence of the error for a signal in lower level is likely to remain.
There is a DEM converter in which, although no detailed configuration thereof is explained here, the unit amounts corresponding to a code are given to all of N local DACs in order in a sampling period Ts so that every local DAC is equally used. Such DEM converter, however, has the following problem.
For quantized levels of N and a noise shaper frequency of fs, at least a frequency of as high as (N*fs) is necessary for the system clock which requires that the audio system provide an expensive system clock. FIG. 4 is a diagram showing a result of simulation carried out in the case where a higher system clock frequency is used under the same error conditions as those in the case shown in FIG. 3. In FIG. 4, the case is shown where a sampling period Ts is finely divided by twelve. In a period of (Ts/12), one level is given to one of LDAC1 to LDAC12 in rotation. This allows all of the local DACs to be equally used even for an output of the quantizer being in one level, so that the output of the converter is fully averaged in a sampling period Ts. In this case, however, a clock with a frequency as high as 12*fs in necessary which increases the cost of the system.
In view of the foregoing, in the present invention, a bit arrangement of the thermometer code is divided into P blocks each being taken as one block for every Q bits, the bit arrangement is shifted in unit of the block in rotation at the sampling frequency fs, the bit arrangement is further shifted in unit of the bit in rotation at a frequency fs*Q and a code output of the shifted code is produced, each of bits of which output is given to the local DAC corresponding to each of the bits. Alternatively, the bit arrangement of the code output, which arrangement is taken as being expressed in terms of a matrix having P rows and Q columns where P represents an arrangement of the blocks and Q represents an arrangement in the block, is converted to a code output expressed in terms of a matrix having Q rows and P columns by interchanging the rows and columns with each other, by which a scattering in space is provided for the local DACs supplied with unit amounts. By means of any one or combination of the two, it is allowed to keep an operating frequency lower and to reduce distortion in the output which is due to change in shifting the data in rotation in the local DACs, which change occurs depending on bit levels of the data in a form of the thermometer code. That is, the present invention solves the problems that arise in conventional DEM converters to allow the realization of a digital-to-analog converter in which improved converting performance is provided without increasing costs.
Thus, the delta sigma digital-to-analog converter is constituted to comprise a set of N one bit local digital to analog converters equally weighted to each other, where N is equal to P times Q and where P and Q are each predetermined integers having a value of at least two; a quantizer having a digital input and an output having P times Q minus one quantized levels at a predetermined sampling frequency fs; a first converter having an input connected to the output of the quantizer for converting the quantizer output to a thermometer code comprising P times Q bits, which thermometer code is provided as an output of the first converter; and a second converter connected to the output of the first converter for receiving the thermometer code, dividing a bit arrangement of the thermometer code into P blocks, each being taken as one block for every Q bits, shifting the bit arrangement in unit of the block in rotation at the sampling frequency fs, further shifting the bit arrangement in unit of the bit in rotation at a frequency fs times Q, and thereby producing a output code on an output of the second converter, which output is, in turn, connected to the local digital to analog converters in corresponding order.
In addition, the delta sigma digital-to-analog converter is also constituted as to comprise a set of N one bit local digital to analog converters equally weighted to each other, where N is equal to P times Q and where P and Q are each predetermined integers having a value of at least two; a quantizer having a digital input and an output having P times Q minus one quantized levels at a predetermined sampling frequency fs; a first converter having an input connected to the output of the quantizer for converting the quantizer output to a thermometer code comprising P times Q bits, which thermometer code is provided on an output of the first converter; and a second converter receiving the thermometer code, dividing a bit arrangement of aid thermometer code into P blocks each being taken as one block for every Q bits, converting the bit arrangement of the temperature code, which arrangement is a matrix having P rows and Q columns where P represents the number of the blocks and Q represents the number of bits in each block, to a code output expressed in terms of a matrix having Q rows and P columns by interchanging the rows and columns, and supplying the code output, expressed in terms of a matrix having Q rows and P columns, as an output of the second converter, which output is connected to the local digital to analog converters in corresponding order.