1. Field of the Invention
The present invention relates generally to the testing of semiconductor wafers during the production of the wafer. More specifically, the present invention relates to the use of a new alignment pattern to determine the registration accuracy between two patterned layers on a semiconductor wafer and image placement accuracy of each patterned layer.
2. Background
One of the most critical process control techniques used in the manufacturing of integrated circuits is the measurement of overlay accuracy between successive, patterned layers on a wafer (i.e., the determination of how accurately a patterned layer aligns with respect to the layer above or below it).
Presently this measurement is done with test patterns that are etched into the layers. The relative displacement is measured by imaging the patterns at high magnification on an electronic camera using any of a variety of known image analysis algorithms. The most commonly used patterns are concentric squares with dimensions of approximately 20 to 40 micrometers on each side, generally referred to as “box within a box” target. FIG. 1 illustrates a typical “box” type target 5. Such targets may be built into scribe lines between adjacent dies on a wafer. An inner box 1 is typically printed on a top layer of the semiconductor wafer being produced, while an open-center-outer box 2 is printed on the second layer down on the semiconductor wafer. The measurement process thus involves imaging target 5 on an electronic camera, by means of a microscope system, at a high magnification (e.g., 1000×, typically) and with high resolution in both x and y directions.
As is generally well known, the overlay error between the two boxes, along the x-axis for example, is determined by calculating the locations of the edges of lines c1 and c2 of the outer box 2, and the edge locations of the lines C3 and C4 of the inner box 1, and then comparing the average separation between lines C1 and C3 with the average separation between lines C2 and C4. Half of the difference between the average separations C1 and C3 and C2 and C4 is the overlay error (along the x-axis). Thus, if the average spacing between lines C1 and C3 is the same as the average spacing between lines C2 and C4, the corresponding overlay error tends to be zero. Although not described, the overlay error between the two boxes along the y-axis may also be determined using the above technique.
This prior art is further described and analyzed by Neal T. Sullivan, “Semiconductor Pattern Overlay”, in Handbook of Critical Dimensions Metrology and Process Control, pp. 160-188, vol. CR52, SPIE Press (1993). The accuracy of this technique is limited by the asymmetry of etched line profiles, by aberrations in the illumination and imaging optics, and by image sampling in the camera. In addition, chemical mechanical planarization (CMP), which is often used in semiconductor manufacturing, can damage such alignment structures. Variations on such box-in-box structures are also described in U.S. Pat. Nos. 6,118,185 and 6,130,750, the disclosures of both of which are incorporated herein by reference.
Partly in response to the above concerns, a grating-type mark was developed. An example of such a mark 10 is shown in FIG. 2. The mark 10 includes a first periodic structure 12 and a second periodic test structure 14. The first periodic test structure 12 is placed on a first layer of a device and the second periodic structure 14 is placed on a second layer of the device adjacent the first periodic structure 12 when the second layer is placed on the first layer. Any offset that may occur between the first and second periodic structures 12, 14 may be detected optically, micro-mechanically or with electron beams. Such grating style targets (sometimes referred to as “AIM” marks) can be denser and more robust, than “box” or ring-type marks resulting in the collection of more process information, as well as target structures that can withstand the rigors of CMP. The use of such marks is described, e.g., by Adel et al in commonly assigned U.S. Pat. Nos. 6,023,338, 6,921,916 and 6,985,618, all three of which are incorporated herein by reference for all purposes.
Unfortunately, as the semiconductor industry uses smaller and smaller design rules, the total error budget for overlay becomes smaller. Part of this error budget includes measurement of both overlay error and a type of error known as image placement error. This latter error is related to the absolute displacement of features of the pattern formed in a layer during a semiconductor fabrication process, usually at the photomask or other tooling used to print the pattern at the wafer level. Unfortunately, grating-type (AIM) marks are not suitable for measurement of this error. Absolute displacement or image placement error measurements require isolated “X” and “Y” edges, which conflict with the dense grating-type marks.
Thus, there is a need in the art, for a new type of alignment mark that overcomes the above disadvantages and a method for using such a mark.