The present invention is in the field of programmable logic devices (PLD""s) and, more particularly, relates to PLD""s having an array of logic elements with a staggered routing architecture such that partial lines result and such partial lines that would otherwise be dangling at interfaces are driven to provide additional signal path flexibility.
Conventional programmable logic devices (PLD""s) comprise an array of logic elements (LE""s), and the routing architecture provides a signal path between LE""s. It is desired to increase the flexibility by which signals can be driven between the PLD core and boundaries of the routing architecture.
In accordance with a broad aspect of the invention, a routing structure in a PLD is implemented in a staggered fashion. Routing lines which would otherwise be xe2x80x9cpartialxe2x80x9d and dangling at a routing architecture boundary are driven, providing additional flexibility for routing signals to the PLD core from the boundaries.