Physical Design Engineer
Need RTL-GDSII engineers with experience in RTL design, Synthesis, Automatic Place and Route (APR), Timing Closure, DRC/LVS expertise. Candidates with experience in performing Equivalence checking (EC) will also be required. Tools and Skills required: ASIC Flow experience, RTL design, Synthesis using Synopsys DC, APR using Synopsys ICC, and EC using Cadence LEC (Conformal). Experience in Advanced process nodes (28nm and below) preferred. EDA Tools knowledge: Synopsys ICC, DC and Primetime. Cadence Conformal LEC The prime responsibility of this position is to either manage a small team of analysts, developers or engineers and drive delivery of a small module of a project ( AD/ AM/ Testing) or serve as entry level specialist with expertise in particular technology /industry domain / a process of a ERP package. If not a module the lead is responsible for functional / technical track of a project.
Title: Physical Design Engineer
Salary: None
Description: Need RTL-GDSII engineers with experience in RTL design, Synthesis, Automatic Place and Route (APR), Timing Closure, DRC/LVS expertise. Candidates with experience in performing Equivalence checking (EC) will also be required. Tools and Skills required: ASIC Flow experience, RTL design, Synthesis using Synopsys DC, APR using Synopsys ICC, and EC using Cadence LEC (Conformal). Experience in Advanced process nodes (28nm and below) preferred. EDA Tools knowledge: Synopsys ICC, DC and Primetime. Cadence Conformal LEC The prime responsibility of this position is to either manage a small team of analysts, developers or engineers and drive delivery of a small module of a project ( AD/ AM/ Testing) or serve as entry level specialist with expertise in particular technology /industry domain / a process of a ERP package. If not a module the lead is responsible for functional / technical track of a project.
Requirements: None experience, None education
Fraudulent: No