Mapping to a floating-point library enables you to synthesize your floating-point design without having to do floating-point to fixed-point conversion. Eliminating the floating-point to fixed-point conversion step reduces the loss of data precision, and enables you to model a
Mapping to a floating-point library enables you to synthesize your floating-point design without having to do floating-point to fixed-point conversion. Eliminating the floating-point to fixed-point conversion step reduces the loss of data precision, and enables you to model a wider dynamic range.
An FPGA floating-point library is a set of floating-point IP blocks that are optimized for synthesis on specific target hardware. Altera® Megafunctions and Xilinx® LogiCORE IP are examples of such libraries.
In the HDL Coder™ block library, a subset of Simulink® blocks support floating-point library mapping. See HDL Coder Support for FPGA Floating-Point Library Mapping.
To map your floating-point design to an Altera or Xilinx FPGA floating-point library:
Set the target device options for your Altera or Xilinx FPGA
synthesis tool using
For example, to set the synthesis tool as
II and chip family as
hdlset_param(model,'SynthesisToolChipFamily','Arria10',... 'SynthesisToolDeviceName','10AS066H2F34E1SG',... 'SynthesisToolPackageName','',... 'SynthesisToolSpeedValue','')
To set up the path to your synthesis tool executable
For example, to set the path to the
Altera Quartus II synthesis
hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath',... 'C:\altera\14.0\quartus\bin\quartus.exe');
Set up your Altera or Xilinx FPGA floating-point simulation libraries. See FPGA Simulation Library Setup.
You can map your Simulink model to floating-point target libraries from the Configuration Parameters dialog box or from the command line.
To map to an FPGA floating-point library:
Open the Configuration Parameters dialog box.
In the HDL Code Generation > Global Settings > Floating Point Target tab, select the floating-point IP library.
For Xilinx LogiCORE® IP, select XILINX LOGICORE as the library. For Altera megafunction IP, you can select ALTERA MEGAFUNCTION (ALTFP) or ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS) as the library.
If you choose ALTERA MEGAFUNCTION (ALTERA FP FUNCTIONS) as the library, the Initialize IP Pipelines to Zero option becomes available. Select the Initialize IP Pipelines to Zero option to initialize pipeline registers in the IP to zero. In the Target and Optimizations pane, enter the target frequency that you want the floating-point IP to map to.
Note: When mapping to ALTERA FP FUNCTIONS, the target language must be set to VHDL.
When you choose the
ALTERA FP FUNCTIONS library,
an IP Configuration table appears. By using the data type table, you
can customize the IP settings of the floating-point target library.
For more information, see Customize the IP Latenc