Non-volatile memory technology, which can hold data with the power removed, has become critical to devices such as PDAs, cell phones, and digital cameras. In the last issue of InfoTracks, we presented the background of one of the original
Non-volatile memory technology, which can hold data with the power removed, has become critical to devices such as PDAs, cell phones, and digital cameras. In the last issue of InfoTracks, we presented the background of one of the original non-volatile memory technologies, the metal nitride oxide silicon (MNOS) technology. Part Two of this informative three-part series will cover an improvement over MNOS called silicon oxide nitride oxide silicon (SONOS) technology, and its predecessor, silicon nitride oxide silicon (SNOS). Next, we’ll discuss the floating gate avalanche injection MOS or FAMOS transistor, used extensively in ultraviolet erasable memory.
While attempting to improve MNOS performance during the 1970s, Takaaki Hagiwara and his colleagues at Hitachi developed the SNOS. They determined that coupling a low pressure chemical vapor deposition silicon nitride with a high- temperature hydrogen anneal of the nitride-ultrathin oxide-silicon interface increased memory retention times to over 10 years. To make the power supply voltage in the read mode compatible with other contemporary standard logic components, Hagiwara et al. reduced the voltage to five volts. They were also able to reduce access times to fewer than 150 nanoseconds--more than six times faster than contemporary MNOS memories. Since performing a high temperature anneal requires temperatures in excess of the aluminum melting point, the technique cannot be performed on memories that utilize aluminum gate technology.
The diagram above depicts the SNOS two-transistor memory cell. The SNOS memory cell permits full byte programming. The gate on the left is the SNOS transistor, while the gate on the right is the select transistor for the memory cell. The ultrathin oxide measures approximately 10 to 20 angstroms and the low pressure CVD silicon nitride measures about 500 angstroms.
The SNOS process requires two polysilicon deposition steps. The first deposition step, poly one, forms the access transistor gates and the rest of the logic gates on the circuit. The second step, poly two, forms the control gate for the SNOS transistor.
Although SNOS devices possess a more efficient write time than MNOS memories, SNOS technology still has limitations. One particular problem is hole injection from the gate. Especially when the nitride is thin, hole injection from the gate can limit the charge retention capabilitie