Over the last couple of years, FPGAs have made amazing advances in performance and capacity. Solutions, such as physical synthesis, are now needed that allow designers to take advantage of these improvements. Given the advancements in FPGAs and high levels
Over the last couple of years, FPGAs have made amazing advances in performance and capacity. Solutions, such as physical synthesis, are now needed that allow designers to take advantage of these improvements. Given the advancements in FPGAs and high levels of performance, past techniques are failing to deliver a design that can close on timing. In many leading-edge designs the traditional approaches are not enough; hence the need for the synthesis algorithms that use physical data to improve the results.
This article discusses the gap between today's tool capabilities and the needed successful timing closure of designs. A call is put out for synthesis algorithms that use physical data to improve the timing closure results.
Timing closure is not simple to achieve. And the solution needs to be robust, yet easy-to-use and accessible to the FPGA designer. ASICs and FPGAs require different implementation strategies, yet both have many things in common. Both use leading-edge technologies, currently 0.13 micron. Both are typically designed with VHDL or Verilog. Both are not shipped until timing is achieved. And finally, both have the ever-increasing challenge of timing closure for designers.
Many EDA vendors are trying to solve the challenge of achieving timing closure in a deep-submicron ASIC. The migration of ASIC designers to FPGAs and the advancements in FPGA architectures are also causing FPGA tool vendors to look seriously at this same challenge. The timing closure challenge in FPGAs is driven by the increase in complexity and performance of the current generation of FPGA devices. Ensuring that performance is achieved with these complex devices-which contain advanced building blocks such as DSP structures, high-speed I/O interfaces, specialized memories and built-in processors-requires a new approach to FPGA synthesis, one aimed specifically at achieving timing closure. The biggest challenge to timing closure is the gap between the physical and logical worlds. For performance reasons, the current generation of synthesis algorithms estimates interconnect delay with wire-load models based on fan-out. With the previous generation of programmable devices and designs, this approach was sufficient because the gate delay accounted for the majorit