[coreboot] 3 questions about coreboot
FENG Yu Ning
fengyuning1984 at gmail.com
Thu Jul 8 07:28:36 CEST 2010
Peter Stuge wrote:
> See
[coreboot] 3 questions about coreboot
FENG Yu Ning
fengyuning1984 at gmail.com
Thu Jul 8 07:28:36 CEST 2010
Peter Stuge wrote:
> See http://stuge.se/pc2010.png for a sketch of the components in a
> contemporary PC.
Great drawing, Peter.
ali, I would like to add some detail.
The picture mentioned by Peter show an architecture that is closer to
the AMD ones, in which memory controller is integrated into the CPU.
The 945 architecture has memory controller in the northbridge.
The bridge chips have logic deciding if the coming address access
should be responsed by it, or should be routed to somewhere else.
As in 945, when an address comes from CPU, the northbridge
decides whether the address access means a memory access,
a configuration to the chip itself, or to other devices that connects
to it. In the case of first instruction address, the northbridge will
pass that request to southbridge.
Read the chipset manual for more information. Some effort is
is needed to extract what you want from the text.
By the way, since my knowledge is still of the single core age
and I know little about architectures other than Intel x86, my
explanation may not be accurate. I think someone in the list
will correct me if that was the case.
More information about the coreboot