In Chapter 6 of the PIC32 book I briefly mention that the PIC32 differs from all previous PIC microcontrollers since it offers a Von Neumann programming model as opposed to the Harvard model adopted by all previous Microchip architectures. Then, in
In Chapter 6 of the PIC32 book I briefly mention that the PIC32 differs from all previous PIC microcontrollers since it offers a Von Neumann programming model as opposed to the Harvard model adopted by all previous Microchip architectures. Then, in a note I remind all the readers that the core of the PIC32 (MIPS M4K) is Harvard based. More than one reader has written back to me to report the apparent contradiction, while in fact there is none. Let’s see if I can make things clearer …
The fact is that we could say that there is a model for the core and a model for the (system) programming of the PIC32.
The M4K core itself IS based on the Harvard model and has two parallel buses (the I bus for instruction fetching and the D bus for data read/write). This way the core can simultaneously fetch a new instruction (from the cache and pre-fetch units) while reading or writing data to RAM.
But contrary to all previous PIC microcontrollers when programming the PIC32 in C language (and even assembly for that matter) the separation between the two buses disappears completely and the PIC32 behaves as a Von Neumann machine. In fact there is a single addressing space where data and program reside and no tricks are required to read data from Flash, for example (in the 8-bit PIC this used to require special retlw instructions and in the 16-bit PIC and dsPIC it used to require a special “window” mechanism called the PSV and/or the use of special instructions tblrd/tblwr once more…). Data and program appear as if coming from the same bus.
The “magic” in the PIC32 is achieved by the “bus matrix” module where the I and D buses coming from the core are joined and arbitrated!
The bus matrix sits between the actual system bus hosting all memories and the peripherals (it’s a single bus – Von Neumann) and the core through the cache (core and cache are connected by the two separate buses I and D – Harvard).
The bus matrix actually does much more than this, as you might have read in chapter 6, including the virtual to physical address translation and kernel/user mode protection.
In summary, the PIC32 is a machine with a Harvard core, but can be programmed as a Von Neuman one. As a consequence you get the best of both:
– you can run code from RAM for example
– you don’t have to use special instructions to read data from FLASH
– you have a single address space, requiring the use of a single type of pointers
– in other words you have the simplicity and convenience of the von Neumann model
At the same time:
– the core can access data and fetch instructions at twice the speed
– the cache can be optimized for data and/or program capacity
– in other words you get the performance boost of a typical Harvard architecture.
Hope this helps…