The heterodyne receiver has been the standard receiver option of choice for decades. In recent years, the rapid advance of analog-to-digital converter (ADC) sampling rates, the inclusion of embedded digital processing, and the integration of matched channels now
The heterodyne receiver has been the standard receiver option of choice for decades. In recent years, the rapid advance of analog-to-digital converter (ADC) sampling rates, the inclusion of embedded digital processing, and the integration of matched channels now offers options for the receiver architect that were not practical only a few years ago.
This article compares the benefits and challenges of three common receiver architectures: a heterodyne receiver, a direct sampling receiver, and a direct-conversion receiver. Additional consideration on spurious system noise and dynamic range is also discussed. The intention is not to promote one option over others—but rather describe the pros and cons of the options, and encourage the designer to select, through engineering discipline, the architecture most appropriate for the application.
Table 1 compares the heterodyne, direct sampling, and direct-conversion architectures. The basic topology is shown along with some of the benefits and challenges of each architecture.
The heterodyne approach is well proven and provides exceptional performance. The implementation is to mix to an intermediate frequency (IF). The IF is chosen at a high enough frequency to allow practical filters in the operating band to provide good image rejection and LO isolation. It is also common to add an additional mixing stage to lower the frequency where very high dynamic range ADCs are available. Additionally, the receiver gain is distributed at different frequencies, which minimizes the risk of oscillation in high gain receivers. Through proper frequency planning, the heterodyne receiver can be made with very good spurious energy and noise performance. Unfortunately, this architecture is the most complicated. It typically requires the most power and the largest physical footprint relative to the available bandwidth. In addition, frequency planning can be quite challenging at large fractional bandwidths. These challenges are significant with the modern quest toward low size, weight, and power (SWaP), combined with the desire for wide bandwidth, and lead to designers considering other architecture options when possible.
The direct sampling approach has long been sought after. The obstacles have been operating the converters at speeds commensurate with direct RF sampling and achieving large input bandwidth. In this architecture, all the receiver gain is at the operating band frequency, so careful layout is required if large receiver gain is desired. Today converters are available for direct sampling in higher Nyquist bands at both L- and S-band. Advances are continuing and C-band sampling will soon be practical, with X-band sampling to follow.
Direct-conversion architectures provide the most efficient use of the data converter bandwidth. The data converters operate in the first Nyquist, where performance is optimum and low-pass filtering is easier. The two data converters work together sampling I/Q signals, thus increasing the user bandwidth without the challenges of interleaving. The dominant challenge that has plagued direct-conversion architecture for years has been to maintain I/Q balance for acceptable levels of image rejection, LO leakage, and dc offsets. In recent years, the advanced integration of the entire direct-conversion signal chain, combined with digital calibrations, has overcome these challenges and the direct-conversion architecture is well positioned to be a very practical approach in many systems.
Frequency Plan Perspective
Figure 1 illustrates block diagrams and frequency plan examples of the three architectures. Figure 1a is an example of a heterodyne receiver with a high-side LO mixing the operating band to the 2nd Nyquist zone of the ADC. The signal is further aliased to the 1st Nyquist zone for processing. Figure 1b shows a direct sampling receiver example. The operating band is sampled in the 3rd Nyquist zone and aliases to the 1st Nyquist, then an NCO is placed in the center of the band, digitally downconverting to baseband, followed by filtering and decimation, reducing the data rate commensurate with the channel bandwidth. Figure 1c is a direct-conversion architecture example. By mating the dual ADC with a quadrature demodulator, Channel 1 samples the I (in phase) signal and Channel 2 samples the Q (quadrature) signal.
Many modern ADCs support all three architectures. For example, the AD9680 is a dual, 1.25 GSPS ADC with programmable digital downconversion. A dual ADC of this type supports 2-channel heterodyne and direct sampling architectures, or the converters can work as a pair in a direct-conversion architecture.
The image rejection challenges of the direct-conversion architecture can be quite difficult to overcome in a discrete implementation. With further integration combined with digitally assisted processing, the I/Q channels can be well matched, leading to much improved image rejection. The receiver section of the recently released AD9371 is a direct-conversion receiver and shown in Figure 2—note the similarity to Figure 1c.
Any design with frequency translation requires much effort to minimize unwanted frequencies folding in-band. This is the art of frequency planning and involves a balance of available components and practical filter design. Some of the spur folding concerns are briefly discussed and the designer is referred to the references for further explanation.
Figure 3 shows the folding of the ADC input frequency and the first two harmonics as a function of input frequency relative to the Nyquist band frequencies. For channel band