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Advanced Micro Devices will add “strained silicon” to its microprocessor lineup this quarter to improve performance, a company spokesman confirmed Friday.
AMD was expected to begin implementing strained silicon in its 90-nm chips, which the company
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Advanced Micro Devices will add “strained silicon” to its microprocessor lineup this quarter to improve performance, a company spokesman confirmed Friday.
AMD was expected to begin implementing strained silicon in its 90-nm chips, which the company has just begun producing from its fab in Dresden, Germany. The addition of the technology of the chips to its older 130-nm process is somewhat of a surprise, although a company representative said AMD tweaks its silicon process on a regular basis; last quarter, the chip company added five incremental improvements, he said.
Strained silicon works by “straining” the lattice of electrical bonds that make up the inside of a chip, pulling them apart slightly. In this way, the amount of drive current needed to power the chip is reduced, allowing the chip to run faster. Intel Corp., which has targeted its strained silicon for its 90-nm process, has said that it can also prevent leakage with its strained silicon technique, which would waste power.
“It’s a different approach to technology transitions,” said Rob Keosheyan, a spokesman for AMD in Austin. “In terms of transistor enhancements, we’re not waiting for major transitions but making subtle enhancements to transistors on average of about one a quarter.”
Keosheyan said the company can roll out the transistor changes to its product lines through a technique called automated precision manufacturing, AMD’s version of the “Copy Exact” procedure that Intel uses to monitor output. AMD’s approach uses tiny sensors that dynamically monitor and tweak the silicon “recipe” used to create chips on a wafer lot-by-lot basis. AMD owns over 250 patents on the APM technology, Keosheyan said.
With the addition of strained silicon, AMD’s 64-bit chips will include a combination of silicon-on-insulator (SOI) as well as strained silicon, improving performance further. Silicon-on-insulator places the transistor’s silicon junction area on top of an electrical insulator, reducing the capacitance and the “charging time” a transistor needs before it can fire. Combining the two process tweaks is much more difficult than simply including one, AMD executives have said.
To date, IBM has been one of the proponents of strained silicon. AMD had previously worked with a company called AmberWave and silicon f